dm9000_st7100.c

在ST7100平台上运行的DM9000驱动程序

/*

  dm9ks.c: Version 1.33 06/08/2005 
  
        A Davicom DM9000A/DM9010 ISA NIC fast Ethernet driver for Linux.
	Copyright (C) 1997 2005  Sten Wang, Jackal Huang

	This program is free software; you can redistribute it and/or
	modify it under the terms of the GNU General Public License
	as published by the Free Software Foundation; either version 2
	of the License, or (at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.


  (C)Copyright 1997-2005 DAVICOM Semiconductor,Inc. All Rights Reserved.

	
V1.00	10/13/2004	Add new function Early transmit & IP/TCP/UDP Checksum
			offload enable & flow control is default
V1.1	12/29/2004	Add Two packet mode & modify RX function
V1.2	01/14/2005	Add Early transmit mode 
V1.3	03/02/2005	Support kernel 2.6
v1.33   06/08/2005	#define DM9KS_MDRAL		0xf4
			#define DM9KS_MDRAH		0xf5 
*/

#if defined(MODVERSIONS)
#include <linux/modversions.h>
#endif

//#define ETRANS

//added by woogy
#ifndef __KERNEL__
#	define __KERNEL__
#endif
//added by woogy init.h config.h sched.h kernel.h slab.h
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/version.h>
#include <asm/dma.h>
#include <linux/spinlock.h>
#include <linux/crc32.h>

//added by woogy 
#include <asm/io.h>
#include <asm/delay.h>

/* Board/System/Debug information/definition ---------------- */

#define DM9KS_ID		0x90000A46
/*-------register name-----------------------*/
#define DM9KS_NCR		0x00	/* Network control Reg.*/
#define DM9KS_NSR		0x01	/* Network Status Reg.*/
#define DM9KS_TCR		0x02	/* TX control Reg.*/
#define DM9KS_RXCR		0x05	/* RX control Reg.*/
#define DM9KS_BPTR		0x08
#define DM9KS_EPCR		0x0b
#define DM9KS_EPAR		0x0c
#define DM9KS_EPDRL		0x0d
#define DM9KS_EPDRH		0x0e
#define DM9KS_GPR		0x1f	/* General purpose register */
#define DM9KS_TCR2		0x2d
#define DM9KS_SMCR		0x2f 	/* Special Mode Control Reg.*/
#define DM9KS_ETXCSR		0x30	/* Early Transmit control/status Reg.*/
#define	DM9KS_TCCR		0x31	/* Checksum cntrol Reg. */
#define DM9KS_RCSR		0x32	/* Receive Checksum status Reg.*/
#define DM9KS_MRCMDX		0xf0
#define DM9KS_MRCMD		0xf2
#define DM9KS_MDRAL		0xf4
#define DM9KS_MDRAH		0xf5
#define DM9KS_MWCMD		0xf8
#define DM9KS_TXPLL		0xfc
#define DM9KS_TXPLH		0xfd
#define DM9KS_ISR		0xfe
#define DM9KS_IMR		0xff
/*---------------------------------------------*/
#define DM9KS_REG05		0x30	/* SKIP_CRC/SKIP_LONG */ 
#define DM9KS_REGFF		0x83	/* IMR */
#define DM9KS_DISINTR		0x80

#define DM9KS_PHY		0x40	/* PHY address 0x01 */
#define DM9KS_PKT_RDY		0x01	/* Packet ready to receive */

//changed by woogy 
#if 0
#define DM9KS_MIN_IO		0x300
#define DM9KS_MAX_IO		0x370
#else
//modify from 0xa2000000 to 0xa1000000 by wsj
#define DM9KS_MIN_IO		0xa1000000
//modify from 0xa2000070 to 0xa1000070 by wsj
#define DM9KS_MAX_IO		0xa1000070

#define DM9000_PPTR   *(volatile u16 *)(DM9KS_MIN_IO)
//modify from DM9KS_MIN_IO+4 to DM9KS_MIN_IO+0x80000 by wsj
#define DM9000_PDATA  *(volatile u16 *)(DM9KS_MIN_IO+0x80000)
#endif

#define DM9KS_VID_L		0x28
#define DM9KS_VID_H		0x29
#define DM9KS_PID_L		0x2A
#define DM9KS_PID_H		0x2B

#define DM9KS_RX_INTR		0x01
#define DM9KS_TX_INTR		0x02

#define DM9KS_DWORD_MODE	1
#define DM9KS_BYTE_MODE		2
#define DM9KS_WORD_MODE		0

#define TRUE			1
#define FALSE			0

#define DMFE_TIMER_WUT  jiffies+(HZ*2)	/* timer wakeup time : 2 second */
#define DMFE_TX_TIMEOUT (HZ*2)		/* tx packet time-out time 1.5 s" */

//#define DM9KS_DEBUG

#if defined(DM9KS_DEBUG)
#define DMFE_DBUG(dbug_now, msg, vaule)  printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
//if (dmfe_debug||dbug_now) printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
#else
#define DMFE_DBUG(dbug_now, msg, vaule)\
if (dbug_now) printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
#endif

#pragma pack(push, 1)
typedef struct _RX_DESC
{
	u8 rxbyte;
	u8 status;
	u16 length;
}RX_DESC;

typedef union{
	u8 buf[4];
	RX_DESC desc;
} rx_t;
#pragma pack(pop)

enum DM9KS_PHY_mode {
	DM9KS_10MHD   = 0, 
	DM9KS_100MHD  = 1, 
	DM9KS_10MFD   = 4,
	DM9KS_100MFD  = 5, 
	DM9KS_AUTO    = 8, 
};

/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
 
	u32 reset_counter;		/* counter: RESET */ 
	u32 reset_tx_timeout;		/* RESET caused by TX Timeout */ 
#if 0
	u16 io_addr;			/* Register I/O base address */
	u16 io_data;			/* Data I/O address */
#else
	u32 io_addr;			/* Register I/O base address */
	u32 io_data;			/* Data I/O address */
#endif
	u16 tx_pkt_cnt;

	u8 op_mode;			/* PHY operation mode */
	u8 io_mode;			/* 0:word, 2:byte */
	u8 device_wait_reset;		/* device state */

	struct timer_list timer;
	struct net_device_stats stats;
	unsigned char srom[128];
	spinlock_t lock;

} board_info_t;

/* Global variable declaration ----------------------------- */
/*static int dmfe_debug = 0;*/
static struct net_device * dmfe_dev = NULL;

/* For module input parameter */
static int mode       = DM9KS_AUTO;
static int media_mode = DM9KS_AUTO;
//chagned by woogy 
#if 0
static u8  irq        = 3;
#else
//modify from irq=2 to irq=5 by wsj because we use irq1
static u8  irq        = 5;
#endif

static u32 iobase     = DM9KS_MIN_IO;
//static u16 iobase     = DM9KS_MIN_IO;

/* function declaration ------------------------------------- */
//added by woogy 
int Dm9ks_init_module(void);
void Dm9ks_cleanup_module(void);
int dmfe_probe(struct net_device *);
static int dmfe_open(struct net_device *);
static int dmfe_start_xmit(struct sk_buff *, struct net_device *);
static void dmfe_tx_done(unsigned long);
static void dmfe_packet_receive(struct net_device *);
static int dmfe_stop(struct net_device *);
static struct net_device_stats * dmfe_get_stats(struct net_device *); 
static int dmfe_do_ioctl(struct net_device *, struct ifreq *, int);
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
static void dmfe_interrupt(int , void *, struct pt_regs *);
#else
static irqreturn_t dmfe_interrupt(int , void *, struct pt_regs *);
#endif
static void dmfe_timer(unsigned long);
static void dmfe_init_dm9000(struct net_device *);
static unsigned long cal_CRC(unsigned char *, unsigned int, u8);
static u8 ior(board_info_t *, int);
static void iow(board_info_t *, int, u8);
static u16 phy_read(board_info_t *, int);
static void phy_write(board_info_t *, int, u16);
static u16 read_srom_word(board_info_t *, int);
static void dm9000_hash_table(struct net_device *);
#if defined(CHECKSUM)
static u8 check_rx_ready(u8);
#endif

//DECLARE_TASKLET(dmfe_tx_tasklet,dmfe_tx_done,0);

/* DM9000 network baord routine ---------------------------- */

/*
  Search DM9000 board, allocate space and register it
*/
struct net_device * __init dmfe_probe1(void)
{
	struct net_device *dev;
	int err;

#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
	dev = init_etherdev(NULL, sizeof(struct board_info));
	ether_setup(dev);		
#else
//changed by woogy 
#if 0
	dev= alloc_etherdev(sizeof(struct board_info));
#else
	dev= alloc_etherdev(sizeof(struct net_device));
#endif
#endif

	if(!dev)
		return ERR_PTR(-ENOMEM);


     	SET_MODULE_OWNER(dev);
	err = dmfe_probe(dev);
	if (err)
		goto out;
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
	err = register_netdev(dev);
	if (err)
		goto out1;
#endif
	return dev;
out1:
	release_region(dev->base_addr,2);
out:
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
	kfree(dev);
#else
	free_netdev(dev);
#endif
	return ERR_PTR(err);
}

static void 
dmfe_timeout(struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;


	db->reset_tx_timeout++;
	db->stats.tx_errors++;
	db->device_wait_reset++;
	
	/* DM9000A/DM9010 dynamic RESET check and do */
	if (db->device_wait_reset) {
		netif_stop_queue(dev); 
		db->reset_counter++;
		db->device_wait_reset = 0;
		dev->trans_start = 0;
		dmfe_init_dm9000(dev);
		netif_wake_queue(dev);
	}
}

int __init dmfe_probe(struct net_device *dev)
{
	struct board_info *db;    /* Point a board information structure */
	u32 id_val;
	u16 i, dm9000_found = FALSE;
	//debug by davicom ,mark by wsj
	//char tmp[1000];
	//int j,k,nsr;
	//debug
	DMFE_DBUG(0, "dmfe_probe()",0);

	//printk("iobase : 0x%x \n",iobase);

	/* Search All DM9000 serial NIC */
	do {
#if 0
		outb(DM9KS_VID_L, iobase);
		id_val = inb(iobase + 4);
		outb(DM9KS_VID_H, iobase);
		id_val |= inb(iobase + 4) << 8;
		outb(DM9KS_PID_L, iobase);
		id_val |= inb(iobase + 4) << 16;
		outb(DM9KS_PID_H, iobase);
		id_val |= inb(iobase + 4) << 24;
#else
		DM9000_PPTR = DM9KS_PID_H;
		id_val = (DM9000_PDATA & 0xff) << 8;
		DM9000_PPTR = DM9KS_PID_L;
		id_val+= (DM9000_PDATA & 0xff);
		id_val = id_val << 16;
	
		DM9000_PPTR = DM9KS_VID_H;
		id_val += (DM9000_PDATA & 0xff) << 8;
		DM9000_PPTR = DM9KS_VID_L;
		id_val += (DM9000_PDATA & 0xff);
#endif		
		printk(">>>> id_val: 0x%x <-> ID: 0x%x\n",id_val,DM9KS_ID);
		printk(">>>> dev->name : %s \n",dev->name);

		if (id_val == DM9KS_ID) {
			
			/* Request IO from system */
			if(!request_region(iobase, 2, dev->name))
				return -ENODEV;

			//printk("<DM9KS> I/O: %x, VID: %x \n",iobase, id_val);
			dm9000_found = TRUE;
      printk("*************DM9000 found:ID= %x,************** \n",id_val);
			/* Allocated board information structure */
			memset(dev->priv, 0, sizeof(struct board_info));
			db = (board_info_t *)dev->priv;
			dmfe_dev    = dev;
			db->io_addr  = iobase;
			db->io_data = iobase + 0x80000;
			/* driver system function */
	
printk("[dm9ks]dev private initialize......\n");
			
			dev->base_addr 		= iobase;
			dev->irq 		= irq;
			dev->open 		= &dmfe_open;
			dev->hard_start_xmit 	= &dmfe_start_xmit;
			dev->watchdog_timeo	= HZ;
			dev->tx_timeout		= dmfe_timeout;
			dev->stop 		= &dmfe_stop;
			dev->get_stats 		= &dmfe_get_stats;
			dev->set_multicast_list = &dm9000_hash_table;
			dev->do_ioctl 		= &dmfe_do_ioctl;

#if defined(CHECKSUM)
			dev->features = dev->features | NETIF_F_NO_CSUM;
#endif

//changed by woogy
#if 0
			/* Read SROM content */
			for (i=0; i<64; i++)
				((u16 *)db->srom)[i] = read_srom_word(db, i);

			/* Set Node Address */
			for (i=0; i<6; i++)
				dev->dev_addr[i] = db->srom[i];
#else

			dev->dev_addr[0]=0x00;
			dev->dev_addr[1]=0x30;
			dev->dev_addr[2]=0x6a;
			dev->dev_addr[3]=0x70;
			dev->dev_addr[4]=0x10;
			dev->dev_addr[5]=0x01;

#endif

		}//end of if()
//removed by woogy 
#if 0
		iobase += 0x10;
	}while(!dm9000_found && iobase <= DM9KS_MAX_IO);
#else
	}while(!dm9000_found);
#endif

//add for debug tx,by davicom ,mark by wsj 
#if 0
	
  for(j=0;j<1000;j++)
  		tmp[j]=(unsigned char)j;
   
   while(1)
   {
   	
	/* Disable all interrupt */
	iow(db, DM9KS_IMR, DM9KS_DISINTR);
	//printk("1");
	/* Set TX length to reg. 0xfc & 0xfd */
	iow(db, DM9KS_TXPLL, (1000 & 0xff));
	//printk("2");
	iow(db, DM9KS_TXPLH, (1000 >> 8) & 0xff);
  //printk("3");
	/* Move data to TX SRAM */
	//data_ptr = (char *)skb->data;

	//outb(DM9KS_MWCMD, db->io_addr); // Write data into SRAM trigger
	DM9000_PPTR = DM9KS_MWCMD;
	//db->sent_pkt_len = skb->len;
  //printk("4");
	switch(db->io_mode)
	{
		case DM9KS_WORD_MODE:
			//tmplen = (1000 + 1) / 2;
			//printk("5");
			for (i = 0,k=0; i < (1000 + 1) / 2; i++,k++)
				DM9000_PDATA =((u16 *)tmp)[k++];
         		break;
		
	}
	//printk("6");
	/* Issue TX polling command */
	iow(db, DM9KS_TCR, 0x1); /* Cleared after TX complete*/
  //printk("7");

	/* Re-enable interrupt */
	iow(db, DM9KS_IMR, DM9KS_REGFF);
	//printk("8");
	nsr = ior(db, DM9KS_NSR);
	//printk("9,--%x--",nsr);
	while(!((nsr & 0x04) || (nsr & 0x08)));
	printk("a\n");
   	
  }
#endif  
   
	return dm9000_found ? 0:-ENODEV;
}

/*
  Open the interface.
  The interface is opened whenever "ifconfig" actives it.
*/
static int dmfe_open(struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	DMFE_DBUG(0, "dmfe_open", 0);

	if (request_irq(dev->irq,&dmfe_interrupt,SA_SHIRQ,dev->name,dev)) 
		return -EAGAIN;

	/* Initilize DM910X board */
	dmfe_init_dm9000(dev);
 
	/* Init driver variable */
	db->reset_counter 	= 0;

#if 0
	/* set and active a timer process */
	init_timer(&db->timer);
	db->timer.expires 	= DMFE_TIMER_WUT * 2;
	db->timer.data 		= (unsigned long)dev;
	db->timer.function 	= &dmfe_timer;
	add_timer(&db->timer);	//Move to DM9000 initiallization was finished.
#endif	
	netif_start_queue(dev);

	return 0;
}

/* Set PHY operationg mode
*/
static void set_PHY_mode(board_info_t *db)
{
	u16 phy_reg0 = 0x1200;		/* Auto-negotiation & Restart Auto-negotiation */
	u16 phy_reg4 = 0x01e1;		/* Default flow control disable*/

	if ( !(db->op_mode & DM9KS_AUTO) ) // op_mode didn't auto sense */
	{ 
		switch(db->op_mode) {
			case DM9KS_10MHD:  phy_reg4 = 0x21; 
                        	           phy_reg0 = 0x1000;
					   break;
			case DM9KS_10MFD:  phy_reg4 = 0x41; 
					   phy_reg0 = 0x1100;
                                	   break;
			case DM9KS_100MHD: phy_reg4 = 0x81; 
					   phy_reg0 = 0x3000;
				    	   break;
			case DM9KS_100MFD: phy_reg4 = 0x101; 
					   phy_reg0 = 0x3100;
				   	   break;
			default: 
					   break;
		} // end of switch
		phy_write(db, 0, phy_reg0);
		phy_write(db, 4, phy_reg4);
	} // end of if
}

/* 
	Initilize dm9000 board
*/
static void dmfe_init_dm9000(struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	DMFE_DBUG(0, "dmfe_init_dm9000()", 0);
//printk(">>> set internal PHY \n");
//printk(" db: 0x%x \n",db);
//printk(" db->io_addr: 0x%x \n",db->io_addr);
//printk(" db->io_data: 0x%x \n",db->io_data);
	/* set the internal PHY power-on, GPIOs normal, and wait 2ms */
	iow(db, DM9KS_GPR, 0);	/* GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY */
	udelay(20);		/* wait 2ms for PHY power-on ready */

//printk(">>> software reset \n");
	/* do a software reset and wait 20us */
	iow(db, DM9KS_NCR, 3);
	udelay(20);		/* wait 20us at least for software reset ok */
	iow(db, DM9KS_NCR, 3);	/* NCR (reg_00h) bit[0] RST=1 & Loopback=1, reset on. Added by SPenser */
	udelay(20);		/* wait 20us at least for software reset ok */

	/* I/O mode */
	db->io_mode = ior(db, DM9KS_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */

	/* Set PHY */
	db->op_mode = media_mode;
	set_PHY_mode(db);

	/* Program operating register */
	iow(db, DM9KS_NCR, 0);
	iow(db, DM9KS_TCR, 0);		/* TX Polling clear */
	iow(db, DM9KS_BPTR, 0x3f);	/* Less 3kb, 600us */
	iow(db, DM9KS_SMCR, 0);		/* Special Mode */
	iow(db, DM9KS_NSR, 0x2c);	/* clear TX status */
	iow(db, DM9KS_ISR, 0x0f); 	/* Clear interrupt status */

	/* Added by jackal at 03/29/2004 */
#if defined(CHECKSUM)
	iow(db, DM9KS_TCCR, 0x07);	/* TX UDP/TCP/IP checksum enable */
	iow(db, DM9KS_RCSR, 0x02);	/*Receive checksum enable */
#endif

#if defined(ETRANS)
	iow(db, DM9KS_ETXCSR, 0x80);
#endif
 
	/* Set address filter table */
	dm9000_hash_table(dev);

	/* Activate DM9000A/DM9010 */
	iow(db, DM9KS_RXCR, DM9KS_REG05 | 1);	/* RX enable */
	iow(db, DM9KS_IMR, DM9KS_REGFF); 	// Enable TX/RX interrupt mask
 
	/* Init Driver variable */
	db->tx_pkt_cnt 		= 0;
	dev->trans_start 	= 0;

	
	netif_carrier_on(dev);
	spin_lock_init(&db->lock);

}

/*
  Hardware start transmission.
  Send a packet to media from the upper layer.
*/
static int dmfe_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	board_info_t *db = (board_info_t *)dev->priv;
	char * data_ptr;
	int i, tmplen;