amijiema.mdl

该程序实现了几种线路码的编译过程。包括编码和译码的过程

  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "AMIjiema"
    Location		    [2, 70, 1022, 718]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      SubSystem
      Name		      "Atomic Subsystem"
      Ports		      [1, 1]
      Position		      [420, 189, 520, 231]
      FontSize		      10
      TreatAsAtomicUnit	      on
      System {
	Name			"Atomic Subsystem"
	Location		[2, 70, 1022, 718]
	Open			on
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [335, 203, 365, 217]
	}
	Block {
	  BlockType		  Reference
	  Name			  "Clock"
	  Ports			  [0, 1]
	  Position		  [235, 301, 275, 329]
	  SourceBlock		  "simulink_extras/Flip Flops/Clock"
	  SourceType		  "Digital clock"
	  MaskParam1		  "0.5"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant"
	  Position		  [235, 390, 265, 420]
	}
	Block {
	  BlockType		  Reference
	  Name			  "J-K\nFlip-Flop"
	  Ports			  [3, 2]
	  Position		  [425, 267, 470, 343]
	  SourceBlock		  "simulink_extras/Flip Flops/J-K\nFlip-Flop"
	  SourceType		  "JKFlipFlop"
	  initial_condition	  "0"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [2, 1]
	  Position		  [550, 202, 580, 233]
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator1"
	  Ports			  [2, 1]
	  Position		  [555, 342, 585, 373]
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator4"
	  Ports			  [2, 1]
	  Position		  [310, 352, 340, 383]
	  Operator		  "OR"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Sum
	  Name			  "Subtract"
	  Ports			  [2, 1]
	  Position		  [660, 300, 700, 340]
	  Inputs		  "+-"
	  ShowAdditionalParam	  on
	  InputSameDT		  off
	  OutDataTypeMode	  "Specify via dialog"
	  OutScaling		  "2^-10"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [750, 313, 780, 327]
	}
	Line {
	  SrcBlock		  "J-K\nFlip-Flop"
	  SrcPort		  1
	  Points		  [15, 0; 0, -60]
	  DstBlock		  "Logical\nOperator"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "J-K\nFlip-Flop"
	  SrcPort		  2
	  Points		  [15, 0; 0, 40]
	  DstBlock		  "Logical\nOperator1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  Points		  [10, 0; 0, -30]
	  DstBlock		  "Logical\nOperator4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Clock"
	  SrcPort		  1
	  Points		  [15, 0]
	  DstBlock		  "Logical\nOperator4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator1"
	  SrcPort		  1
	  Points		  [25, 0; 0, -30]
	  DstBlock		  "Subtract"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  Points		  [30, 0; 0, 90]
	  DstBlock		  "Subtract"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    Points		    [0, 95]
	    DstBlock		    "J-K\nFlip-Flop"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [115, 0]
	    Branch {
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Branch {
	      Points		      [0, 140]
	      DstBlock		      "Logical\nOperator1"
	      DstPort		      1
	    }
	  }
	}
	Line {
	  SrcBlock		  "Logical\nOperator4"
	  SrcPort		  1
	  Points		  [40, 0; 0, -40]
	  Branch {
	    Points		    [0, -50]
	    DstBlock		    "J-K\nFlip-Flop"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "J-K\nFlip-Flop"
	    DstPort		    3
	  }
	}
	Line {
	  SrcBlock		  "Subtract"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Bernoulli Binary\nGenerator"
      Ports		      [0, 1]
      Position		      [165, 148, 245, 192]
      FontName		      "Arial"
      SourceBlock	      "commrandsrc2/Bernoulli Binary\nGenerator"
      SourceType	      "Bernoulli Binary Generator"
      P			      "0.5"
      seed		      "61"
      Ts		      "0.5"
      frameBased	      off
      sampPerFrame	      "1"
      orient		      off
    }
    Block {
      BlockType		      Reference
      Name		      "Clock"
      Ports		      [0, 1]
      Position		      [175, 276, 215, 304]
      SourceBlock	      "simulink_extras/Flip Flops/Clock"
      SourceType	      "Digital clock"
      MaskParam1	      "0.5"
    }
    Block {
      BlockType		      Constant
      Name		      "Constant"
      Position		      [525, 260, 555, 290]
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator1"
      Ports		      [2, 1]
      Position		      [580, 192, 615, 258]
      AllPortsSameDT	      off
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator2"
      Ports		      [2, 1]
      Position		      [305, 192, 335, 223]
      AllPortsSameDT	      off
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [2]
      Position		      [670, 142, 720, 233]
      Location		      [188, 365, 512, 604]
      Open		      off
      NumInputPorts	      "2"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
      }
      List {
	ListType		SelectedSignals
	axes1			""
	axes2			""
      }
      YMin		      "-5~-5"
      YMax		      "5~5"
      DataFormat	      "StructureWithTime"
    }
    Line {
      SrcBlock		      "Bernoulli Binary\nGenerator"
      SrcPort		      1
      Points		      [20, 0; 0, 30]
      DstBlock		      "Logical\nOperator2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Clock"
      SrcPort		      1
      Points		      [15, 0; 0, -75]
      DstBlock		      "Logical\nOperator2"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Logical\nOperator2"
      SrcPort		      1
      Points		      [25, 0]
      Branch {
	DstBlock		"Atomic Subsystem"
	DstPort			1
      }
      Branch {
	Points			[0, -45]
	DstBlock		"Scope"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Atomic Subsystem"
      SrcPort		      1
      DstBlock		      "Logical\nOperator1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Constant"
      SrcPort		      1
      Points		      [0, -35]
      DstBlock		      "Logical\nOperator1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Logical\nOperator1"
      SrcPort		      1
      Points		      [15, 0; 0, -15]
      DstBlock		      "Scope"
      DstPort		      2
    }
  }
}