cmijiema.mdl

来自「该程序实现了几种线路码的编译过程。包括编码和译码的过程」· MDL 代码 · 共 668 行 · 第 1/2 页

	  BlockType		  Reference
	  Name			  "Clock"
	  Ports			  [0, 1]
	  Position		  [235, 301, 275, 329]
	  SourceBlock		  "simulink_extras/Flip Flops/Clock"
	  SourceType		  "Digital clock"
	  MaskParam1		  "0.5"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant"
	  Position		  [415, 205, 445, 235]
	}
	Block {
	  BlockType		  Reference
	  Name			  "D Flip-Flop"
	  Ports			  [3, 2]
	  Position		  [475, 117, 520, 193]
	  SourceBlock		  "simulink_extras/Flip Flops/D Flip-Flop"
	  SourceType		  "DFlipFlop"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [2, 1]
	  Position		  [390, 136, 420, 169]
	  Operator		  "NAND"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator1"
	  Ports			  [2, 1]
	  Position		  [450, 292, 480, 323]
	  Operator		  "NAND"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator2"
	  Ports			  [2, 1]
	  Position		  [670, 202, 700, 233]
	  Operator		  "NAND"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator3"
	  Ports			  [2, 1]
	  Position		  [585, 112, 615, 143]
	  Operator		  "NAND"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator4"
	  Ports			  [1, 1]
	  Position		  [315, 299, 345, 331]
	  Operator		  "NOT"
	  Inputs		  "1"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator5"
	  Ports			  [1, 1]
	  Position		  [390, 249, 420, 281]
	  Operator		  "NOT"
	  Inputs		  "1"
	  AllPortsSameDT	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [770, 213, 800, 227]
	}
	Line {
	  SrcBlock		  "Logical\nOperator5"
	  SrcPort		  1
	  Points		  [5, 0; 0, 35]
	  DstBlock		  "Logical\nOperator1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator3"
	  SrcPort		  1
	  Points		  [15, 0; 0, 80]
	  DstBlock		  "Logical\nOperator2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator1"
	  SrcPort		  1
	  Points		  [85, 0; 0, -85]
	  DstBlock		  "Logical\nOperator2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical\nOperator4"
	  SrcPort		  1
	  Points		  [0, 0; 25, 0]
	  Branch {
	    DstBlock		    "Logical\nOperator1"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Logical\nOperator"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "D Flip-Flop"
	  SrcPort		  2
	  Points		  [10, 0; 0, -75; -75, 0]
	  DstBlock		  "D Flip-Flop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "D Flip-Flop"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "D Flip-Flop"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [135, 0]
	  Branch {
	    DstBlock		    "Logical\nOperator"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, -60; 195, 0; 0, 35]
	    DstBlock		    "Logical\nOperator3"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 120]
	    DstBlock		    "Logical\nOperator5"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  Points		  [5, 0; 0, -40]
	  DstBlock		  "D Flip-Flop"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Clock"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator2"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Bernoulli Binary\nGenerator"
      Ports		      [0, 1]
      Position		      [115, 113, 195, 157]
      FontName		      "Arial"
      SourceBlock	      "commrandsrc2/Bernoulli Binary\nGenerator"
      SourceType	      "Bernoulli Binary Generator"
      P			      "0.5"
      seed		      "61"
      Ts		      "0.5"
      frameBased	      off
      sampPerFrame	      "1"
      orient		      off
    }
    Block {
      BlockType		      Reference
      Name		      "Clock"
      Ports		      [0, 1]
      Position		      [280, 261, 320, 289]
      SourceBlock	      "simulink_extras/Flip Flops/Clock"
      SourceType	      "Digital clock"
      MaskParam1	      "0.5"
    }
    Block {
      BlockType		      Constant
      Name		      "Constant1"
      Position		      [535, 180, 565, 210]
    }
    Block {
      BlockType		      Reference
      Name		      "D Flip-Flop1"
      Ports		      [3, 2]
      Position		      [610, 132, 655, 208]
      SourceBlock	      "simulink_extras/Flip Flops/D Flip-Flop"
      SourceType	      "DFlipFlop"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator6"
      Ports		      [1, 1]
      Position		      [385, 119, 415, 151]
      Operator		      "NOT"
      Inputs		      "1"
      AllPortsSameDT	      off
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator7"
      Ports		      [2, 1]
      Position		      [480, 127, 510, 158]
      Operator		      "OR"
      AllPortsSameDT	      off
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [2]
      Position		      [775, 89, 825, 211]
      Location		      [188, 365, 512, 604]
      Open		      off
      NumInputPorts	      "2"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
      }
      List {
	ListType		SelectedSignals
	axes1			""
	axes2			""
      }
      YMin		      "-5~-5"
      YMax		      "5~5"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      UnitDelay
      Name		      "Unit Delay"
      Position		      [390, 185, 425, 225]
      X0		      "1"
      SampleTime	      "0.25"
    }
    Block {
      BlockType		      UnitDelay
      Name		      "Unit Delay1"
      Position		      [390, 255, 425, 295]
      SampleTime	      "0.255"
    }
    Line {
      SrcBlock		      "Bernoulli Binary\nGenerator"
      SrcPort		      1
      Points		      [10, 0]
      Branch {
	DstBlock		"Atomic Subsystem"
	DstPort			1
      }
      Branch {
	Points			[0, -60; 485, 0; 0, 45]
	DstBlock		"Scope"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Logical\nOperator6"
      SrcPort		      1
      DstBlock		      "Logical\nOperator7"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Unit Delay"
      SrcPort		      1
      Points		      [15, 0; 0, -55]
      DstBlock		      "Logical\nOperator7"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Logical\nOperator7"
      SrcPort		      1
      DstBlock		      "D Flip-Flop1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Constant1"
      SrcPort		      1
      DstBlock		      "D Flip-Flop1"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Unit Delay1"
      SrcPort		      1
      Points		      [145, 0; 0, -105]
      DstBlock		      "D Flip-Flop1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Atomic Subsystem"
      SrcPort		      1
      Points		      [20, 0]
      Branch {
	DstBlock		"Logical\nOperator6"
	DstPort			1
      }
      Branch {
	Points			[0, 70]
	DstBlock		"Unit Delay"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Clock"
      SrcPort		      1
      DstBlock		      "Unit Delay1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "D Flip-Flop1"
      SrcPort		      1
      Points		      [50, 0; 0, 30]
      DstBlock		      "Scope"
      DstPort		      2
    }
  }
}