📄 hw.h
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///////////////////////////////////////////////////////////////////////////////
//
// (C) Copyright 1995 - 1998 OSR Open Systems Resources, Inc.
// All Rights Reserved
// Based on a previous work by Microsoft Corporation
// Copyright (c) 1991, 1992, 1993 Microsoft Corporation
//
// This sofware is supplied for instructional purposes only.
//
// OSR Open Systems Resources, Inc. (OSR) expressly disclaims any warranty
// for this software. THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY
// OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION,
// THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A PARTICULAR
// PURPOSE. THE ENTIRE RISK ARISING FROM THE USE OF THIS SOFTWARE REMAINS
// WITH YOU. OSR's entire liability and your exclusive remedy shall not
// exceed the price paid for this material. In no event shall OSR or its
// suppliers be liable for any damages whatsoever (including, without
// limitation, damages for loss of business profit, business interruption,
// loss of business information, or any other pecuniary loss) arising out
// of the use or inability to use this software, even if OSR has been
// advised of the possibility of such damages. Because some states/
// jurisdictions do not allow the exclusion or limitation of liability for
// consequential or incidental damages, the above limitation may not apply
// to you.
//
// This driver is the example Programmed I/O device driver that
// accompanies the book Windows NT Device Driver Development, by
// Peter Viscarola and W. Anthony Mason, (c) 1998 OSR Open Systems
// Resources, Inc. and published by MacMillan Technical Publishing
// ISBN 1578700582.
//
// MODULE:
//
// $Workfile: hw.h $
//
// ABSTRACT:
//
// This module handles the
//
// AUTHOR:
//
// Open Systems Resources, Inc.
//
// REVISION:
//
///////////////////////////////////////////////////////////////////////////////
//
// This module contains the HW interface definitions
//
#ifndef HW_H
#define HW_H
//
// ST506 register definitions, as offsets from a base (which should be
// passed in by configuration management).
//
#define DATA_REGISTER 0
#define WRITE_PRECOMP_REGISTER 1
#define ERROR_REGISTER 1
#define SECTOR_COUNT_REGISTER 2
#define SECTOR_NUMBER_REGISTER 3
#define CYLINDER_LOW_REGISTER 4
#define CYLINDER_HIGH_REGISTER 5
#define DRIVE_HEAD_REGISTER 6
#define COMMAND_REGISTER 7
#define STATUS_REGISTER 7
//
// In addition to I/O space access to the controller registers, ISA defines
// a separate "drive control" register. Here's commands to send to that
// register.
//
#define RESET_CONTROLLER 0x04
#define ENABLE_INTERRUPTS 0x00
//
//
#define DRIVE_PARAMETER_TABLE_LENGTH 0x01bfe
//
// Configuration Memory equates. These are used to determine how many
// drives are attached to the system (you send a query, ie
// CFGMEM_HARD_DRIVES_TYPE, out the CFGMEM_QUERY_PORT, and then read the
// type in from CFGMEM_DATA_PORT - if the type is 0, then there is no disk
// attached).
//
#define CFGMEM_QUERY_PORT (PUCHAR)0x70
#define CFGMEM_DATA_PORT (PUCHAR)0x71
#define CFGMEM_FIRST_CONTROLLER_DRIVE_TYPES (UCHAR)0x12
#define CFGMEM_DRIVES_FIRST_DRIVE_MASK 0xf0
//
// ISA defines the following vectors to hold pointers to fixed disk
// parameter tables - this allows us to determine the types of drives
// on the system.
//
#define PTR_TO_FDPT0_ADDRESS 0x41 * sizeof (ULONG)
#define PTR_TO_FDPT1_ADDRESS 0x46 * sizeof (ULONG)
//
// When we're resetting the controller, we have to go through some states
// as various operations finish (that is, interrupt). Here's the states
// in order.
//
#define RESET_NOT_RESETTING 0
#define RESET_DRIVE_SET 1
#define RESET_DRIVE_RECALIBRATED 2
//
// ST506 controller commands for the command register.
//
#define READ_COMMAND 0x20 // retries enabled
#define READ_MULTIPLE 0xC4
#define WRITE_COMMAND 0x30 // retries enabled
#define WRITE_MULTPLE 0xC5
#define SET_MULTIPLE_MODE 0xC6
#define RECALIBRATE_COMMAND 0x10 // move drive heads to track 0
#define SEEK_COMMAND 0x70 // normally implied in read/write
#define SET_DRIVE_PARAMETERS_COMMAND 0x91 // set drive parameters
#define IDENTIFY_COMMAND 0xEC // identify drive parameters
//
// ST506 controller bit masks for the status register.
//
#define BUSY_STATUS 0x80 // busy bit in status register
#define ERROR_STATUS 0x01 // error bit in status register
#define CORRECTED_ERROR_STATUS 0x04 // corrected error in status register
#define DATA_REQUEST_STATUS 0x08 // data request bit in status register
//
// ST506 controller bit masks for the drive select/head register.
//
#define DRIVE_1 0xA0 // drive 1 (C:), 512 bytes/sector
// DRIVE/HEAD port, ext bit on
#endif /* HW_H */
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