fredivn1.vhd

全是FPGA的例子 对大家应该有好处 大家赶快下把 知识不等人

--odd frequency division

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fredivn1 is
	GENERIC (N:integer:=15);
port (clk:in std_logic;
		outclk:out std_logic);
end fredivn1;

architecture rtl of fredivn1 is
signal count1,count2:integer;
signal q,outclk1,outclk2:std_logic;
begin
q<=outclk1 and outclk2;

outclk<=q xor outclk1;

process(clk)
begin 
	if(clk'event and clk='1') then
	if(count1=N-1)then
			count1<=0;
	else
	
			count1<=count1+1;
		if count1<(integer(N/2)) then
			outclk1<='0';
		else
			outclk1<='1';
		end if;
	end if;
	end if;
end process;
process(clk)
begin
	if(clk'event and clk='0') then
	if(count2=N-1)then
			count2<=0;
	else
	
			count2<=count2+1;
		if count2<(integer(N/2)) then
			outclk2<='1';
		else
			outclk2<='0';
		end if;
	end if;
	end if;
end process;		
		
end rtl;