key_scan.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity key_scan is
port(clk,key_pre:in std_logic;
		row:in std_logic_vector(3 downto 0);
		com:out std_logic_vector(3 downto 0);
		scan_code:out std_logic_vector(7 downto 0));
end key_scan;
architecture behav of key_scan is
signal sig_com:std_logic_vector(3 downto 0);
signal counter:std_logic_vector(1 downto 0);
signal tmp_1,sig_1,sig_2,sig_3,sig_4,sig_5:std_logic;
component dff2
port(clk,cd,sd,d:in std_logic;
				q,notq:out std_logic);
end component;
begin
sig_3<='1';
sig_4<=not tmp_1;
tmp_1<=row(0) and row(1) and row(2) and row(3);
u1:dff2
port map(key_pre,sig_4,sig_4,sig_4,sig_2,sig_5);
process(clk)
variable temp :std_logic;
begin
if(clk'event and clk='1')then
if(sig_1='1')then
	temp:=sig_com(3);
	for i in 3 downto 1 loop
		sig_com(i)<=sig_com(i-1);
	end loop;
	sig_com(0)<=temp;
else 
	sig_com<="1110";
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
if(sig_1='1')then
com<=sig_com;
else 
com<="0000";
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
if(sig_1='1')then
if(counter="11")then
counter<="00";
else
counter<=counter+'1';
end if;
else
counter<="00";
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
if(sig_2='1')then
if(counter="11")then
sig_1<='0';
else
sig_1<='1';
end if;
else
sig_1<='0';
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
if(sig_1='1')then
if(tmp_1='0')then
scan_code<=row & sig_com;
else 
scan_code<="11111111";
end if;
else
scan_code<="11111111";
end if;
end if;
end process;
end behav;