cdeled10.vhd

全是FPGA的例子 对大家应该有好处 大家赶快下把 知识不等人

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cDELED10 IS
PORT( LIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      cs:in std_logic;
      LOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
     );
END cDELED10;

ARCHITECTURE BEHAV OF cDELED10 IS
BEGIN
PROCESS(LIN,cs)
BEGIN 
if cs='0' then
   lout<="1111111";
elsif LIN="0000" then LOUT<="1000000";
elsif lin="0001" then LOUT<="1001111";
elsif lin="0010" then LOUT<="0100100";
elsif lin="0011" then LOUT<="0110000";
elsif lin="0100" then LOUT<="0011001";
elsif lin="0101" then LOUT<="0010010";
elsif lin="0110" then LOUT<="0000010";
elsif lin="0111" then LOUT<="1111000";
elsif lin="1000" then LOUT<="0000000";
elsif lin="1001" then LOUT<="0010000";
else  LOUT<="1111111";
end if;
END PROCESS;
END BEHAV;