division.vhd

来自「全是FPGA的例子 对大家应该有好处 大家赶快下把 知识不等人」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity division is
port(
		div_in:in std_logic;
		div_cnt:in unsigned(7 downto 0);
		div_out:out std_logic);
end division;

architecture behav of division is 
begin
 	process
  		variable cnt:unsigned(7 downto 0);
  	begin
  			wait until div_in'event and div_in='1';
  				cnt:=cnt+1;
  			if cnt=div_cnt then
  				div_out<='1';
  				cnt:="00000000";
			else 
				div_out<='0';
 			end if;
  		end process;
  	end behav;