📄 hd_sep_demo.vhd
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-- Internal LED control signals
signal mr_tx2_led_out : std_logic;
signal mr_tx1_led_out : std_logic;
signal mr_rx_led_out : std_logic;
signal asi_tx_led_out : std_logic;
signal sdi_rx_led_out : std_logic;
signal sdi_tx_led_out : std_logic;
signal mr_sync_led_out : std_logic;
signal mr_hd_led_out : std_logic;
signal mr_rate_led_out : std_logic;
signal sdi_sync_led_out : std_logic;
signal sdi_rate_led_out : std_logic;
signal mode_mr_led_out : std_logic;
signal mode_sdi_led_out : std_logic;
signal mode_asi_led_out : std_logic;
-- Signals for HD-SDI receiver
signal rx_recclk : std_logic; -- recovered clock from RocketIO receiver
signal rx_usrclk : std_logic; -- rx_recclk after BUFG
signal rx_refclksel : std_logic; -- selects Rx reference clock
signal rx_data : hd_vid20_type; -- data from RocketIO receiver
signal rx_nsp : std_logic; -- new start position from framer
signal rx_vid_y : hd_video_type; -- Y channel received video
signal rx_vid_c : hd_video_type; -- C channel received video
signal rx_format : hd_vidstd_type; -- decoded video standard from hdsdi_autodetect_ln
signal rx_locked : std_logic; -- hdsdi_autodetect_ln is locked
signal clr_errs : std_logic; -- clear the error LED
signal crc_err_ff : std_logic; -- captures CRC errors
signal rx_y_crc_err : std_logic; -- Y channel CRC error from hdsdi_rx
signal rx_c_crc_err : std_logic; -- C channel CRC error from hdsdi_rx
signal rx_crc_err : std_logic; -- OR of Y and C CRC errors
signal rx_trs_err : std_logic; -- TRS error signal
signal rx_xyz : std_logic; -- xyz output of hdsdi_rx
signal rx_sav : std_logic; -- sav output of hdsdi_rx
signal rx_eav : std_logic; -- eav output of hdsdi_rx
signal rx_field : std_logic; -- field output from hdsdi_rx_timing
signal rx_v_blank : std_logic; -- v_blank output from hdsdi_rx_timing
signal rx_h_blank : std_logic; -- h_blank output from hdsdi_rx_timing
signal heartbeat : std_logic; -- receiver heartbeat signal for LED
signal rx_ln : hd_vpos_type; -- rx line number
-- Signals for HD-SDI transmitter
signal tx_usrclk : std_logic; -- global transmitter clock (BUFGMUX output)
signal tx_refclksel : std_logic; -- RocketIO reference clock select
signal stdsel_reg : std_logic_vector(2 downto 0); -- input register for the standard select inputs
signal stdsel_syncreg : std_logic_vector(2 downto 0); -- synchronization register for std select inputs
signal tx_vid_y : hd_video_type; -- video pat gen Y channel output
signal tx_vid_c : hd_video_type; -- video pat gen C channel output
signal tx_ln : hd_vpos_type; -- video pat gen line number output
signal tx_xyz : std_logic; -- video pat gen XYZ word indicator
signal tx_eav : std_logic; -- EAV signal into transmitter
signal tx_sav : std_logic; -- SAV signal into transmitter
signal tx_data : hd_vid20_type; -- encoded data to RocketIO transmitter
signal tx_force_crc_err : std_logic; -- forces a CRC on Tx2 output
signal tx_patsel : std_logic_vector(1 downto 0); -- pattern select for video pattern gen
signal tx_insert_logo : std_logic; -- Xilinx logo enable for pattern gen
attribute IOSTANDARD : string;
attribute IOSTANDARD of HDXO1 : label is "LVDSEXT_25_DT";
attribute IOSTANDARD of HDXOM : label is "LVDSEXT_25_DT";
begin
--
-- Instantiate the startup block so that push_button1 drives the global reset
--
STARTV2 : STARTUP_VIRTEX2
port map (
CLK => '0',
GSR => n_button1,
GTS => '0');
-------------------------------------------------------------------------------
-- I/O Buffers
--
--
-- Push button switches
--
-- PB1 is global reset
-- PB2 resets the CRC error LED
-- PB3 forces CRC transmission errors out MR-Tx2
--
PB1 : IBUF_LVCMOS25
port map (
I => push_button1,
O => button1);
PB2 : IBUF_LVCMOS25
port map (
I => push_button2,
O => button2);
PB3 : IBUF_LVCMOS25
port map (
I => push_button3,
O => button3);
n_button1 <= not button1;
clr_errs <= not button2;
tx_force_crc_err <= not button3;
--
-- DIP switches
--
SW0 : IBUF_LVCMOS25
port map (
I => dip_switches(0),
O => dipsw(0));
SW1 : IBUF_LVCMOS25
port map (
I => dip_switches(1),
O => dipsw(1));
SW2 : IBUF_LVCMOS25
port map (
I => dip_switches(2),
O => dipsw(2));
SW3 : IBUF_LVCMOS25
port map (
I => dip_switches(3),
O => dipsw(3));
SW4 : IBUF_LVCMOS25
port map (
I => dip_switches(4),
O => dipsw(4));
SW5 : IBUF_LVCMOS25
port map (
I => dip_switches(5),
O => dipsw(5));
SW6 : IBUF_LVCMOS25
port map (
I => dip_switches(6),
O => dipsw(6));
SW7 : IBUF_LVCMOS25
port map (
I => dip_switches(7),
O => dipsw(7));
tx_refclksel <= dipsw(0);
--
-- LED Buffers
--
LED0 : OBUF_LVCMOS25
port map (
I => mr_tx2_led_out,
O => mr_tx2_led);
LED1 : OBUF_LVCMOS25
port map (
I => mr_tx1_led_out,
O => mr_tx1_led);
LED2 : OBUF_LVCMOS25
port map (
I => mr_rx_led_out,
O => mr_rx_led);
LED3 : OBUF_LVCMOS25
port map (
I => asi_tx_led_out,
O => asi_tx_led);
LED4 : OBUF_LVCMOS25
port map (
I => sdi_rx_led_out,
O => sdi_rx_led);
LED5 : OBUF_LVCMOS25
port map (
I => sdi_tx_led_out,
O => sdi_tx_led);
LED6 : OBUF_LVCMOS25
port map (
I => mr_sync_led_out,
O => mr_sync_led);
LED7 : OBUF_LVCMOS25
port map (
I => mr_hd_led_out,
O => mr_hd_led);
LED8 : OBUF_LVCMOS25
port map (
I => mr_rate_led_out,
O => mr_rate_led);
LED9 : OBUF_LVCMOS25
port map (
I => sdi_sync_led_out,
O => sdi_sync_led);
LED10 : OBUF_LVCMOS25
port map (
I => sdi_rate_led_out,
O => sdi_rate_led);
LED11 : OBUF_LVCMOS25
port map (
I => mode_mr_led_out,
O => mode_mr_led);
LED12 : OBUF_LVCMOS25
port map (
I => mode_sdi_led_out,
O => mode_sdi_led);
LED13 : OBUF_LVCMOS25
port map (
I => mode_asi_led_out,
O => mode_asi_led);
--
-- GS1528 Cable Driver slew rate control output
--
-- The GS1528 cable driver has a slew rate control input that tells it whether
-- to compliant with SDI or HD-SDI slew rates. In this demo, we are always
-- transmitting HD-SDI, so we always force this signal low.
--
MRTX2_SLEW : OBUF_LVCMOS33
port map (
I => '0',
O => mr_tx2_slewrate);
MRTX1_SLEW : OBUF_LVCMOS33
port map (
I => '0',
O => mr_tx1_slewrate);
--
-- 74.25M XO input buffer
--
HDXO1 : IBUFGDS
port map (
O => clk_74_25M,
I => clk_74_25M_p,
IB => clk_74_25M_n);
--
-- 74.1758MHz XO input buffer
--
HDXOM : IBUFGDS
port map (
O => clk_74_17M,
I => clk_74_17M_p,
IB => clk_74_17M_n);
--
-- BUFGMUX to generate tx_usrclk
--
BFG1 : BUFGMUX
port map (
I0 => clk_74_17M,
I1 => clk_74_25M,
S => tx_refclksel,
O => tx_usrclk);
--
-- 33MHz clock input buffer
--
-- The 33 MHz clock is only used for LED control.
--
XO33 : IBUF_LVCMOS25
port map (
O => clk_33M,
I => clk_33M_in);
BUFG33M : BUFG
port map (
O => gclk_33M,
I => clk_33M);
ACECLKEN : OBUF_LVCMOS25
port map (
O => ace_clk_en,
I => '0');
--
-- LED control block
--
LEDC : led_control
port map (
clk => gclk_33M,
mr_tx2_on => '1',
mr_tx2_fast => '0',
mr_tx2_slow => '0',
mr_tx1_on => '0',
mr_tx1_fast => '0',
mr_tx1_slow => '0',
mr_rx_on => heartbeat,
mr_rx_fast => '0',
mr_rx_slow => '0',
asi_tx_on => '0',
asi_tx_fast => '0',
asi_tx_slow => '0',
sdi_rx_on => '0',
sdi_rx_fast => '0',
sdi_rx_slow => '0',
sdi_tx_on => '0',
sdi_tx_fast => '0',
sdi_tx_slow => '0',
mr_sync_on => rx_locked,
mr_sync_fast => '0',
mr_sync_slow => not rx_locked,
mr_hd_on => rx_refclksel,
mr_hd_fast => '0',
mr_hd_slow => '0',
mr_rate_on => rx_format(3),
mr_rate_fast => '0',
mr_rate_slow => '0',
sdi_sync_on => rx_format(2),
sdi_sync_fast => '0',
sdi_sync_slow => '0',
sdi_rate_on => rx_format(1),
sdi_rate_fast => '0',
sdi_rate_slow => '0',
mode_mr_on => rx_format(0),
mode_mr_fast => '0',
mode_mr_slow => '0',
mode_sdi_on => '0',
mode_sdi_fast => '0',
mode_sdi_slow => '0',
mode_asi_on => '0',
mode_asi_fast => crc_err_ff,
mode_asi_slow => '0',
mr_tx2_led => mr_tx2_led_out,
mr_tx1_led => mr_tx1_led_out,
mr_rx_led => mr_rx_led_out,
asi_tx_led => asi_tx_led_out,
sdi_rx_led => sdi_rx_led_out,
sdi_tx_led => sdi_tx_led_out,
mr_sync_led => mr_sync_led_out,
mr_hd_led => mr_hd_led_out,
mr_rate_led => mr_rate_led_out,
sdi_sync_led => sdi_sync_led_out,
sdi_rate_led => sdi_rate_led_out,
mode_mr_led => mode_mr_led_out,
mode_sdi_led => mode_sdi_led_out,
mode_asi_led => mode_asi_led_out
);
-------------------------------------------------------------------------------
-- HD-SDI Receiver Section
--
--
-- RocketIO Transceiver
--
-- This is the RocketIO transceiver. Inside this module are bit-swappers
-- needed to match the bit order of HD-SDI (LSB first) to the bit order of
-- the Rocket IO module (MSB first).
--
RIO1 : hdsdi_rio
port map (
brefclk => clk_74_17M,
brefclk2 => clk_74_25M,
refclk => '0',
refclk2 => '0',
refclk_sel => rx_refclksel,
rst => '0',
loopback_en => '0',
loopback_mode => '0',
txinhibit => '1',
txdata => "00000000000000000000",
txusrclk => rx_usrclk,
txusrclk2 => rx_usrclk,
rxusrclk => rx_usrclk,
rxusrclk2 => rx_usrclk,
dcm_locked => '1',
rxp => mr_rx_rxp,
rxn => mr_rx_rxn,
rxdata => rx_data,
rxrecclk => rx_recclk,
txp => mr_tx1_txp,
txn => mr_tx1_txn);
RXCLK_BUFG : BUFG
port map (
O => rx_usrclk,
I => rx_recclk);
--
-- HD-SDI receiver
--
-- This module decscrambles and frames the data received by the RocketIO
-- receiver. The recovered data is checked for errors.
--
RX : hdsdi_rx
port map (
clk => rx_usrclk,
ce => '1',
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