📄 hd_sep_demo.vhd
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--------------------------------------------------------------------------------
-- Copyright (c) 2004 Xilinx, Inc.
-- All Rights Reserved
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
-- \ \ Filename: $RCSfile: hd_sep_demo.vhd,rcs $
-- / / Date Last Modified: $Date: 2004-12-09 14:39:10-07 $
-- /___/ /\ Date Created: May 25, 2004
-- \ \ / \
-- \___\/\___\
--
--
-- Revision History:
-- $Log: hd_sep_demo.vhd,rcs $
-- Revision 1.1 2004-12-09 14:39:10-07 jsnow
-- XAPP577 version 1 release.
--
-- Revision 1.0 2004-08-26 15:08:07-06 jsnow
-- Translated from Verilog.
--
--------------------------------------------------------------------------------
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE.
--
--------------------------------------------------------------------------------
-- Description of module:
--
-- This is the top level file for the SDV board HD-SDI separate Rx & Tx demo.
--
-- This demo has one HD-SDI transmitter driven from an internal video pattern
-- generator. It also has a separate HD-SDI receiver that will receive the
-- HD-SDI bitstream and check it for CRC errors. The Rx & Tx sections are totally
-- independent. Both interfaces support both HD-SDI bit rates. The receiver
-- automatically detects the bit rate of the incoming bitstream and adjusts to
-- receive it. The transmitter's bit rate is controlled by a DIP switch.
--
-- The DIP switches on the SDV board perform the following functions in this demo:
--
-- SW0: Determines the bit rate of the MR-Tx2 transmitter
-- OFF: 1.485 Gbps
-- ON: 1.485/1.001 Gbps
--
-- SW[2:1]: Determine the video pattern transmitted by the MR-Tx2 transmitter
-- OFF OFF: RP-198 HD-SDI checkfield (pathological patterns)
-- OFF ON: 75% color bars
-- ON OFF: SMPTE RP-219 color bars without Xilinx logo
-- ON ON: SMPTE RP-219 color bars with Xilinx logo inserted
--
-- SW3[4:2] Controls optional user selectable fields in the SMPTE RP-219 video
-- pattern
--
-- SW[7:5]: Determine the video format output by the MR-Tx2 transmitter
-- OFF OFF OFF: SMPTE 296M - 720p 60 Hz or 59.94 Hz
-- OFF OFF ON: SMPTE 274M - 1080p 24 Hz or 23.98 Hz
-- OFF ON OFF: SMPTE 274M - 1080p 25 Hz
-- OFF ON ON: SMPTE 274M - 1080p 30 Hz & 29.97 Hz
-- ON OFF OFF: SMPTE 274M - 1080i 25 Hz
-- ON OFF ON: SMPTE 274M - 1080i 30 Hz & 29.97 Hz
-- ON ON OFF: SMPTE 274M - 1080sF 24 Hz & 23.98 Hz
-- ON ON ON: SMPTE 295M - 1080i 25 Hz (1250 lines/frame)
--
-- The pushbutton switches on the SDV board have the following functions:
--
-- SW2: FPGA global reset
-- SW3: Clear the receiver CRC error LED
-- SW4: Force a CRC error in the video transmitted by MR-Tx2
--
-- Received CRC errors are indicated by the flashing of the leftmost LED
-- immediately below the pushbuttons. Once a single CRC error is detected, this
-- LED will continue to flash until cleared by pushing pushbutton SW3.
--
-- The LED above the MR-Rx BNC connector will flash when video is being received.
-- This LED indicates the detection of valid TRS symbols in the video and is used
-- as a "heartbeat" indication -- showing that data is being received.
--
-- Some video related signals are output to the J13 testpoints:
--
-- Pin 1: The recovered clock from the MR-Rx receiver (before jitter reduction)
-- Pin 2: CRC error (not latched) -- pulses every time a CRC error is detected
-- Pin 3: Field indicator from received video
-- Pin 4: Vertical blanking indicator from received video
-- Pin 5: Horizontal blanking indicator from received video
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.hdsdi_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity hd_sep_demo is
port (
-- Clock inputs
clk_74_25M_p: in std_logic; -- 74.25MHz XO
clk_74_25M_n: in std_logic;
clk_74_17M_p: in std_logic; -- 74.1758MHz XO
clk_74_17M_n: in std_logic;
clk_33M_in: in std_logic; -- 33 MHz XO
-- Clock control outputs
ace_clk_en: out std_logic; -- 33MHz clock enable
-- Switch inputs
push_button1: in std_logic;
push_button2: in std_logic;
push_button3: in std_logic;
dip_switches: in std_logic_vector(7 downto 0);
-- HD-SDI serial inputs, outputs, and slew rate control
mr_rx_rxp: in std_logic; -- Rocket IO receiver input
mr_rx_rxn: in std_logic;
mr_tx1_txp: out std_logic; -- this RocketIO output pair is unused
mr_tx1_txn: out std_logic;
mr_tx1_slewrate: out std_logic; -- slew rate control for cable driver
mr_tx2_txp: out std_logic; -- Rocket IO transmitter output #2
mr_tx2_txn: out std_logic;
mr_tx2_slewrate: out std_logic; -- slew rate control for cable driver
mr_rx2_rxp: in std_logic; -- this RocketIO input pair is unused
mr_rx2_rxn: in std_logic;
-- LEDs
mr_tx2_led: out std_logic;
mr_tx1_led: out std_logic;
mr_rx_led: out std_logic;
asi_tx_led: out std_logic;
sdi_rx_led: out std_logic;
sdi_tx_led: out std_logic;
mr_sync_led: out std_logic;
mr_hd_led: out std_logic;
mr_rate_led: out std_logic;
sdi_sync_led: out std_logic;
sdi_rate_led: out std_logic;
mode_mr_led: out std_logic;
mode_sdi_led: out std_logic;
mode_asi_led: out std_logic;
-- Test outputs
test_point: out std_logic_vector(9 downto 0);
-- Outputs unused in this demo but required to be driven on the SDV Demo board
sdi_vco_up: out std_logic;
sdi_vco_down: out std_logic;
vcxo_27M_up: out std_logic;
vcxo_27M_down: out std_logic;
vcxo_27M_sel: out std_logic;
ics660_s: out std_logic_vector(3 downto 0);
ics660_x1: out std_logic;
cypll_oe: out std_logic;
cypll_s2: out std_logic;
cypll_sclk: out std_logic;
cypll_sdat: out std_logic;
ics8745_clkout_p: out std_logic;
ics8745_clkout_n: out std_logic;
ics8745_sel: out std_logic_vector(3 downto 0);
ics8745_pll_sel: out std_logic;
ics8745_mr: out std_logic;
sdi_tx_dout_p: out std_logic;
sdi_tx_dout_n: out std_logic;
asi_tx_p: out std_logic;
asi_tx_n: out std_logic;
rs232_txd: out std_logic;
rs232_rts: out std_logic
);
end hd_sep_demo;
architecture synth of hd_sep_demo is
-------------------------------------------------------------------------------
-- Component definitions
--
component led_control is
port (
clk : in std_logic;
mr_tx2_on : in std_logic;
mr_tx2_fast : in std_logic;
mr_tx2_slow : in std_logic;
mr_tx1_on : in std_logic;
mr_tx1_fast : in std_logic;
mr_tx1_slow : in std_logic;
mr_rx_on : in std_logic;
mr_rx_fast : in std_logic;
mr_rx_slow : in std_logic;
asi_tx_on : in std_logic;
asi_tx_fast : in std_logic;
asi_tx_slow : in std_logic;
sdi_rx_on : in std_logic;
sdi_rx_fast : in std_logic;
sdi_rx_slow : in std_logic;
sdi_tx_on : in std_logic;
sdi_tx_fast : in std_logic;
sdi_tx_slow : in std_logic;
mr_sync_on : in std_logic;
mr_sync_fast : in std_logic;
mr_sync_slow : in std_logic;
mr_hd_on : in std_logic;
mr_hd_fast : in std_logic;
mr_hd_slow : in std_logic;
mr_rate_on : in std_logic;
mr_rate_fast : in std_logic;
mr_rate_slow : in std_logic;
sdi_sync_on : in std_logic;
sdi_sync_fast : in std_logic;
sdi_sync_slow : in std_logic;
sdi_rate_on : in std_logic;
sdi_rate_fast : in std_logic;
sdi_rate_slow : in std_logic;
mode_mr_on : in std_logic;
mode_mr_fast : in std_logic;
mode_mr_slow : in std_logic;
mode_sdi_on : in std_logic;
mode_sdi_fast : in std_logic;
mode_sdi_slow : in std_logic;
mode_asi_on : in std_logic;
mode_asi_fast : in std_logic;
mode_asi_slow : in std_logic;
mr_tx2_led : out std_logic;
mr_tx1_led : out std_logic;
mr_rx_led : out std_logic;
asi_tx_led : out std_logic;
sdi_rx_led : out std_logic;
sdi_tx_led : out std_logic;
mr_sync_led : out std_logic;
mr_hd_led : out std_logic;
mr_rate_led : out std_logic;
sdi_sync_led : out std_logic;
sdi_rate_led : out std_logic;
mode_mr_led : out std_logic;
mode_sdi_led : out std_logic;
mode_asi_led : out std_logic;
clk_1Hz : out std_logic
);
end component;
component hdsdi_rio is
port (
brefclk: in std_logic; -- BREFCLK
brefclk2: in std_logic; -- BREFCLK2
refclk: in std_logic; -- REFCLK
refclk2: in std_logic; -- REFCLK2
refclk_sel: in std_logic; -- selects between BREFCLK and BREFCLK2
rst: in std_logic; -- reset signal
loopback_en: in std_logic; -- loopback enable
loopback_mode: in std_logic; -- 0 is serial, 1 is parallel mode
txinhibit: in std_logic; -- inhibits transmitter when 1
txdata: in hd_vid20_type; -- data to be transmitted
txusrclk: in std_logic; -- transmitter usr clock
txusrclk2: in std_logic; -- transmitter usr clock 2
rxusrclk: in std_logic; -- receiver usr clock
rxusrclk2: in std_logic; -- receiver usr clock 2
dcm_locked: in std_logic; -- DCM for RXUSRCLKs is locked
rxp: in std_logic; -- serial input - true
rxn: in std_logic; -- serial input - complement
rxdata: out hd_vid20_type; -- received data from RocketIO receiver
rxrecclk: out std_logic; -- clock recovered by RocketIO receiver
txp: out std_logic; -- serial output - true
txn: out std_logic -- serial output - complement
);
end component;
component hdsdi_rx is
port (
clk: in std_logic; -- receiver clock
rst: in std_logic; -- async reset
ce: in std_logic; -- clock enable
dec_bypass: in std_logic; -- high bypasses the HD-SDI decoder
frame_en: in std_logic; -- framer enable input
rxdata: in hd_vid20_type; -- input data bus
c_out: out hd_video_type; -- chroma channel data output
y_out: out hd_video_type; -- luma channel data output
nsp: out std_logic; -- new start position output
trs: out std_logic; -- asserted during TRS symbols
xyz: out std_logic; -- asserted during XYZ word of TRS symbols
eav: out std_logic; -- asserted during XYZ word of an EAV
sav: out std_logic; -- asserted during XYZ word of an SAV
trs_err: out std_logic; -- asserted during XYZ when error is detected
c_ln: out hd_vpos_type; -- received C channel line number
y_ln: out hd_vpos_type; -- received Y channel line number
c_crc_err: out std_logic; -- C channel CRC error
y_crc_err: out std_logic; -- Y channel CRC error
c_ln_err: out std_logic; -- C channel LN error
y_ln_err: out std_logic; -- Y channel LN error
std: out hd_vidstd_type; -- 4-bit output code from video format detector
std_locked: out std_logic); -- indicates when std is valid
end component;
component hdsdi_rx_autorate is
port (
clk: in std_logic; -- rxusrclk input
rst: in std_logic; -- async reset
sav: in std_logic; -- must be asserted during XYZ of SAV symbols
trs_err: in std_logic; -- TRS error bit from framer
y_crc_err: in std_logic; -- Y channel CRC error
c_crc_err: in std_logic; -- C channel CRC error
refclksel: out std_logic); -- output: 0 = 74.1758 MHz, 1 = 74.25 MHz
end component;
component hdsdi_rx_timing is
port (
clk: in std_logic; -- clock input
rst: in std_logic; -- async reset input
ln_in: in hd_vpos_type; -- line number input
vid_in: in hd_video_type; -- either Y or C channel video input
xyz: in std_logic; -- input asserted during XYZ of TRS
sav: in std_logic; -- input asserted during SAV of TRS
frame_start: out std_logic; -- asserted during h blank when ln = 1
field: out std_logic; -- field indicator
v_blank: out std_logic; -- asserted during vertical blanking interval
h_blank: out std_logic; -- asserted during horizontal blanking interval
horz_position: out hd_hpos_type -- 12-bit horizontal position
);
end component;
component rx_heartbeat is
port (
clk : in std_logic; -- clock input
xyz : in std_logic; -- indicates XYZ word of TRS
trs_err : in std_logic; -- indicates a TRS reception error
heartbeat : out std_logic -- heartbeat output
);
end component;
component multigenHD_logo is
port (
clk: in std_logic; -- video clock
rst: in std_logic; -- async resest
ce: in std_logic; -- clock enable
std: in std_logic_vector(2 downto 0); -- video standard select
pattern: in std_logic_vector(1 downto 0); -- selects pattern type (colorbars or checkfield)
user_opt: in std_logic_vector(1 downto 0); -- selects colorbars options
insert_logo: in std_logic; -- 1 = insert xilinx logo
y: out hd_video_type; -- Y channel output
c: out hd_video_type; -- C channel output
h_blank: out std_logic; -- horizontal blanking indicator
v_blank: out std_logic; -- vertical blanking indicator
field: out std_logic; -- field indicator
trs: out std_logic; -- asserted during 4 words of TRS
xyz: out std_logic; -- asserted during XYZ of TRS
line_num: out hd_vpos_type -- current vertical line number
);
end component;
component hdsdi_tx_path is
port (
clk: in std_logic; -- clock input
rst: in std_logic; -- async reset input
ce: in std_logic; -- clock enable input
c_in: in hd_video_type; -- chroma channel data input
y_in: in hd_video_type; -- luma channel data input
nrzi: in std_logic; -- high enables NRZ-to-NRZ conversion
scram: in std_logic; -- high enables SMPTE 292M scrambler
insert_crc: in std_logic; -- high enables generation & insertion of CRCs
force_crc_err: in std_logic; -- high forces CRC error to be generated
insert_ln: in std_logic; -- high enables line number insertion
ln: in hd_vpos_type; -- line numbers to be inserted
eav: in std_logic; -- input asserted during XYZ word of EAV symbol
sav: in std_logic; -- input asserted during XYZ word of SAV symbol
q: out hd_vid20_type -- encoded data output
);
end component;
-------------------------------------------------------------------------------
-- Signal definitions
--
-- Clock signals
signal clk_74_25M : std_logic; -- 74.25MHz clock after IOB
signal clk_74_17M : std_logic; -- 74.1758MHz clock after IOB
signal clk_33M : std_logic; -- 33MHz clock after IOB
signal gclk_33M : std_logic; -- global 33MHz clock
-- Switch signals
signal dipsw : std_logic_vector(7 downto 0); -- DIP switches after IOBs
signal button1 : std_logic; -- push-button 1 after IOB
signal n_button1 : std_logic; -- inverse of button1
signal button2 : std_logic; -- push-button 2 after IOB
signal button3 : std_logic; -- push-button 3 after IOB
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