📄 multigenhd_logo.vhd
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constant HRGN_SAV1 : hrgn_type -- SAV1 horizontal region
:= std_logic_vector(TO_UNSIGNED(19, HRGN_WIDTH));
constant LOGO_C_COMP : hd_video_type -- Logo is monochrome with C comps always 512
:= std_logic_vector(TO_UNSIGNED(512, hd_video_type'length));
-------------------------------------------------------------------------------
-- Signal definitions
--
signal std_q : std_logic_vector(2 downto 0); -- register for std inputs
signal std_change : std_logic; -- difference between std and std_q
signal h_region : hrgn_type; -- current horizontal region
signal v_inc : std_logic; -- increments the vertical counter
signal h_counter_lsb : std_logic; -- LSB of h_counter
signal trs_int : std_logic; -- horz section TRS output
signal xyz_int : std_logic; -- horz section XYZ output
signal h_int : std_logic; -- horz section H output
signal v_counter : hd_vpos_type; -- vertical counter
signal h_counter : hd_hpos_type; -- horizontal counter
signal v_band : vband_type; -- current vertical band
signal f_int : std_logic; -- vert section F output
signal v_int : std_logic; -- vert section V output
signal first_line : std_logic; -- vert section output indicating first active
signal y_ramp_inc_sel : std_logic; -- vert section output that selects Y-Ramp increment value
signal y_int : hd_video_type; -- Y output of color ROM
signal c_int : hd_video_type; -- C output of color ROM
signal trs_reg : std_logic_vector(1 downto 0); -- TRS signal delay reg
signal xyz_reg : std_logic_vector(1 downto 0); -- XYZ signal delay reg
signal h_reg : std_logic_vector(1 downto 0); -- H delay register
signal v_reg : std_logic_vector(1 downto 0); -- V delay register
signal f_reg : std_logic_vector(1 downto 0); -- F delay register
signal c_reg : hd_video_type;
signal y_reg : hd_video_type;
signal delay_rst : std_logic_vector(15 downto 0); -- reset delay register
signal reset : std_logic; -- internal reset signal
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal GND4 : std_logic_vector(3 downto 0) := "0000";
signal GND32 : std_logic_vector(31 downto 0) := (others => '0');
signal is720p : std_logic; -- asserted for 720p
signal is1080i : std_logic; -- asserted for 1080i
signal is1080p : std_logic; -- asserted for 1080p
signal sav : std_logic; -- asserted during second word of SAV
signal logo_start_v : hd_vpos_type; -- MUX output indicating starting V line of logo
signal logo_end_v : hd_vpos_type; -- MUX output indicating ending V line of logo
signal logo_v_mux : hd_vpos_type; -- MUXes logo_start_v and logo_end_v
signal logo_v_match : std_logic; -- v_counter == logo_v_match comparator output
signal logo_start_h : hd_hpos_type; -- MUX output indicating starting H position of logo
signal rom_adr_v : std_logic_vector(6 downto 0); -- logo ROM V address counter
signal rom_adr_h : std_logic_vector(8 downto 0); -- logo ROM H address counter
signal rom_adr_mult : std_logic_vector(14 downto 0); -- output of multiplier (computes rom_adr_v * LOGO_WIDTH)
signal rom_adr : std_logic_vector(14 downto 0); -- complete logo ROM address
signal arom_adr : std_logic_vector(14 downto 0); -- equal to rom_adr
signal brom_adr : std_logic_vector(14 downto 0); -- set to all zeros
signal arom_adr_ms_dly : std_logic_vector(3 downto 0); -- delayed MSBs of rom address for MUX
signal logo_en_v : std_logic; -- asserted when in logo active region vertically
signal logo_en : std_logic; -- asserted when in logo active region
signal logo_en_dly : std_logic; -- logo_en delayed by one clock cycle
signal logo_Y : hd_video_type; -- logo Y component
signal logo_out_mux_Y : hd_video_type; -- MUX logo Y with video Y
signal logo_out_mux_C : hd_video_type; -- MUX logo C with video C
signal logo_mult_p : std_logic_vector(35 downto 0); -- ROM address multiplier output
signal logo_mult_a : std_logic_vector(17 downto 0); -- ROM address multiplier input A
signal logo_mult_b : std_logic_vector(17 downto 0); -- ROM address multiplier input B
signal logo_mult2_p : std_logic_vector(35 downto 0); -- logo Y scaler mult output
signal logo_mult2_a : std_logic_vector(17 downto 0); -- logo Y scaler mult input A
signal logo_mult2_b : std_logic_vector(17 downto 0); -- logo Y scaler mult input B
signal logo_Y_sum : std_logic_vector(17 downto 0); -- logo Y scaler ouput
signal arom0_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom1_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom2_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom3_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom4_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom5_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom6_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom7_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom8_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom9_out : std_logic_vector(7 downto 0); -- logo ROM
signal arom10_out : std_logic_vector(7 downto 0); -- logo ROM
signal lrom_out : std_logic_vector(7 downto 0); -- MUX selects between logo ROMs
component multigenHD_vert
port (
clk: in std_logic; -- video clock
rst: in std_logic; -- async reset
ce: in std_logic; -- clock enable
std: in std_logic_vector(2 downto 0); -- video standard select
pattern: in std_logic_vector(1 downto 0); -- selects pattern type (colorbars or checkfield)
h_counter_lsb: in std_logic; -- LSB of horizontal counter
v_inc: in std_logic; -- causes the vertical counter to increment
v_band: out vband_type; -- vertical band code output
v : out std_logic; -- vertical blanking indicator
f : out std_logic; -- field indicator
first_line: out std_logic; -- asserted during first active line
y_ramp_inc_sel: out std_logic; -- controls Y-Ramp increment selection
line_num: out hd_vpos_type -- current vertical line number
);
end component;
component multigenHD_horz_logo
port (
clk: in std_logic; -- video clock
rst: in std_logic; -- async reset
ce: in std_logic; -- clock enable
std: in std_logic_vector(2 downto 0); -- video standard select
pattern: in std_logic_vector(1 downto 0); -- selects pattern type (colorbars or checkfield)
user_opt: in std_logic_vector(1 downto 0); -- selects colorbars options
first_line: in std_logic; -- asserted during first active video line
f : in std_logic; -- odd/even field indicator
v_inc: out std_logic; -- increment vertical counter
trs: out std_logic; -- asserted during 4 words of TRS
xyz: out std_logic; -- asserted during XYZ word of TRS
h: out std_logic; -- horizontal blanking interval indicator
h_region: out hrgn_type; -- horizontal region code
h_counter_lsb: out std_logic; -- LSB of horizontal counter
h_counter: out hd_hpos_type -- horizontal counter
);
end component;
component multigenHD_output
port (
clk: in std_logic; -- video clock
rst: in std_logic; -- async reset
ce: in std_logic; -- clock enable
h_region: in hrgn_type; -- horizontal region
v_band: in vband_type; -- vertical band
h_counter_lsb: in std_logic; -- LSB of horizontal counter
y_ramp_inc_sel: in std_logic; -- controls the Y-Ramp increment MUX
y: out hd_video_type; -- luma output channel
c: out hd_video_type -- C channel output
);
end component;
--component MULT18X18
-- port (
-- P : out std_logic_vector (35 downto 0);
-- A : in std_logic_vector (17 downto 0);
-- B : in std_logic_vector (17 downto 0)
-- );
--end component;
component RAMB16_S9_S9
generic (
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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