rx_heartbeat.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: rx_heartbeat.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-08-26 15:05:40-06 $
-- /___/   /\    Date Created: August 24, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: rx_heartbeat.vhd,rcs $
-- Revision 1.0  2004-08-26 15:05:40-06  jsnow
-- Translated from Verilog.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
--
-- This module is used to generate a strobe signal to an LED to be used as a
-- heartbeat indicator, showing that the receiver is receiving video. The module
-- simply takes the TRS signal, decoding externally to this module, uses it as a
-- clock signal and divides it down to to about 2Hz. The heartbeat output of the
-- module can then be connected to an LED for a visible heartbeat indicator.
-- 
-- The module divides the TRS signal by 40960. This will result in a fash rate 
-- of between around 2 Hz, depending the video standard being received. The on 
-- pulse has a less than 50% duty cycle.
--
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

library unisim; 
use unisim.vcomponents.all; 

entity rx_heartbeat is
port (
    clk :           in  std_logic;          -- clock input
    xyz :           in  std_logic;          -- indicates XYZ word of TRS
    trs_err :       in  std_logic;          -- indicates a TRS reception error
    heartbeat :     out std_logic           -- heartbeat output
);
end rx_heartbeat;

architecture synth of rx_heartbeat is

attribute init : string;
attribute init of srl1 : label is "0001";
attribute init of srl2 : label is "0001";
attribute init of srl3 : label is "0001";
attribute init of srl4 : label is "0001";

--
-- Internal signals
--
signal ce1 :            std_logic;                      -- stage 1 clock enable
signal ce2 :            std_logic;                      -- stage 2 clock enable
signal ce3 :            std_logic;                      -- stage 3 clock enable
signal ce4 :            std_logic;                      -- stage 4 clock enable
signal stage1 :         std_logic;                      -- stage 1 output
signal stage2 :         std_logic;                      -- stage 2 output
signal stage3 :         std_logic;                      -- stage 3 output
signal stage4 :         std_logic;                      -- stage 4 output
signal sync :           std_logic_vector(1 downto 0);   -- dual rank synchronizer
signal trs_err_latch :  std_logic;                      -- input to synchronizer
signal good_trs :       std_logic;                      -- used to generate trs_err_latch

begin
    
-- 
-- Generate a synchronous input to the divider circuit that is asserted when
-- the valid XYZ word of a TRS is detected.
-- 

good_trs <= xyz and not trs_err;

process(clk, good_trs)
begin
    if good_trs = '1' then
        trs_err_latch <= '1';
    elsif clk'event and clk='1' then
        trs_err_latch <= '0';
    end if;
end process;

process(clk)
begin
    if clk'event and clk='1' then
        sync <= (sync(0) & trs_err_latch);
    end if;
end process;        

--
-- First stage divider
--
ce1 <= sync(0);

srl1 : SRL16E 
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage1,
        A0  => '1',
        A1  => '1',
        A2  => '1',
        A3  => '1',
        CE  => ce1,
        CLK => clk,
        D   => stage1);
--
-- Second stage divider
--   
ce2 <= ce1 and stage1;

srl2 : SRL16E 
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage2,
        A0  => '1',
        A1  => '1',
        A2  => '1',
        A3  => '1',
        CE  => ce2,
        CLK => clk,
        D   => stage2);
--
-- Third stage divider
--   
ce3 <= ce1 and stage1 and stage2;

srl3 : SRL16E 
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage3,
        A0  => '1',
        A1  => '1',
        A2  => '1',
        A3  => '1',
        CE  => ce3,
        CLK => clk,
        D   => stage3);
--
-- Fourth stage divider
--   
ce4 <= ce1 and stage1 and stage2 and stage3;

srl4 : SRL16E 
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage4,
        A0  => '1',
        A1  => '1',
        A2  => '1',
        A3  => '1',
        CE  => ce4,
        CLK => clk,
        D   => stage4);


heartbeat <= stage4;

end synth;