pd_hd_vcxo.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: Leondard Dieguez, Xilinx, Inc.
--  \   \        Filename: $RCSfile: pd_HD_VCXO.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-08-26 15:05:09-06 $
-- /___/   /\    Date Created: August 25, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: pd_HD_VCXO.vhd,rcs $
-- Revision 1.0  2004-08-26 15:05:09-06  jsnow
-- Translated from Verilog.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
--
-- Description of module:
-- 
-- This module is the low level of the phase detector used in conjuction with an
-- external VCXO and loop filter to implement a PLL for jitter reducing the
-- recovered clock from the Rocket IO transceiver in a HD-SDI pass-through
-- application.
-- 
-------------------------------------------------------------------------------- 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

library unisim; 
use unisim.vcomponents.all; 

entity pd_HD_VCXO is
    port (
        vco:            in  std_logic;
        refclk:         in  std_logic;
        reset:          in  std_logic;
        vcoisfast:      out std_logic;
        vcoisslow:      out std_logic;
        vco_tc:         out std_logic;
        refclk_tc:      out std_logic);
end pd_HD_VCXO;

architecture synth of pd_HD_VCXO is

signal vcoisfast_int :      std_logic;
signal vcoisslow_int :      std_logic;
signal pd_rst :             std_logic;
signal vcocount :           std_logic_vector(7 downto 2);
signal vcocntlow :          std_logic_vector(3 downto 0);
signal vco_tc_int :         std_logic;
signal vcocntlow_tc :       std_logic;
signal refclkcount :        std_logic_vector(7 downto 2);
signal refclkcntlow :       std_logic_vector(3 downto 0);
signal refclk_tc_int :      std_logic;
signal refclkcntlow_tc :    std_logic;

attribute INIT : string;
attribute INIT of pdrst_and2_0 : label is "8";

begin

-------------------------------------------------------------------------------
-- divide counter,  
-- divide vcxo (74.25MHz) by 74 to get ~1MHz the comparison 
-- frequency.
-- 128 - 55(0x37; 7'b011_0111) + 1 = 74 .
--
vco_tc_int <= vcocount(7) or reset ;
vco_tc <= vco_tc_int;
vcocntlow_tc <= vcocntlow(3) ;

process(vco)
begin
    if vco'event and vco='1' then
        if vco_tc_int = '1' then
            vcocount <= "001101";
        elsif vcocntlow_tc = '1' then
            vcocount <= vcocount + 1;
        end if;
    end if;
end process;


-------------------------------------------------------------------------------
-- lower 2 bits of the vco counter.
-- shift reg counter is one hot code;
-- bit 0 is 2'b00
-- bit 1 is 2'b01
-- bit 2 is 2'b10
-- bit 3 is 2'b11
--
process(vco)
begin
    if vco'event and vco='1' then
        if vco_tc_int = '1' then
            vcocntlow <= "1000";
        else
            vcocntlow <= (vcocntlow(2 downto 0) & vcocntlow(3));
        end if;
    end if;
end process;

-------------------------------------------------------------------------------

refclk_tc_int <= refclkcount(7) or reset;
refclk_tc <= refclk_tc_int;
refclkcntlow_tc <= refclkcntlow(3);

-------------------------------------------------------------------------------
-- ref clock divider
-- divide the ref clock (74.25MHz) by 74 to get compare freq of ~1MHz
-- 128 - 55(0x37; 7'b011_0111) + 1 = 74 
--
process(refclk)
begin
    if refclk'event and refclk='1' then
        if refclk_tc_int = '1' then
            refclkcount <= "001101";
        elsif refclkcntlow_tc = '1' then
            refclkcount <= refclkcount + 1;
        end if;
    end if;
end process;

-------------------------------------------------------------------------------
-- lower 2 bits of the ref counter.
-- shift reg counter is one hot code;
-- bit 0 is 2'b00
-- bit 1 is 2'b01
-- bit 2 is 2'b10
-- bit 3 is 2'b11
--
process(refclk)
begin
    if refclk'event and refclk='1' then
        if refclk_tc_int = '1' then
            refclkcntlow <= "1000";
        else
            refclkcntlow <= (refclkcntlow(2 downto 0) & refclkcntlow(3));
        end if;
    end if;
end process;

------------------------------------------------------------------------------
--phase detect for reference
--
-- set on the rising edge of the vco /ref
-- pdetfast is active when the vco is faster than the ref xtal
-- pdetslow is active when the vco is slower than the ref xtal
--
pdfastreg : FDC
    port map (
        D   => '1',
        C   => vco_tc_int,
        CLR => pd_rst,
        Q   => vcoisfast_int);

pdslowreg : FDC
    port map (
        D   => '1',
        C   => refclk_tc_int,
        CLR => pd_rst,
        Q   => vcoisslow_int);

pdrst_and2_0 : LUT2
-- synthesis attribute translate_off
    generic map (
        INIT => "1000") 
-- synthesis attribute translate_on     
    port map (
        I0  => vcoisfast_int,
        I1  => vcoisslow_int,
        O   => pd_rst);

vcoisfast <= vcoisfast_int;
vcoisslow <= vcoisslow_int;

end synth;