hdsdi_rx_timing.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: hdsdi_rx_timing.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-12-09 14:53:04-07 $
-- /___/   /\    Date Created: May 28, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: hdsdi_rx_timing.vhd,rcs $
-- Revision 1.1  2004-12-09 14:53:04-07  jsnow
-- Cosmetic changes only.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
-- 
-- Description of module:
-- 
-- This module is a simple HD-SDI video decoder module. It will generate various
-- video timing outputs. It is not a sophisticated video flywheel decoder. It 
-- relies of video line number information that has been extracted from the 
-- video by the hdsdi_rx_crc module.    This module is not required for the 
-- basic HD-SDI receiver. It is provided here in case some downstream video 
-- processing needs the timing information that it can generate.
-- 
-- The outputs generated by this module are:
-- 
-- frame_start: This output indicates when a new frame is starting. It is 
-- asserted during the entire horizontal blanking intervarl of line number 1.
-- 
-- field: This is captured F bit from the last  TRS symbol.
-- 
-- v_blank: This is the captured V bit from the last TRS symbol.
-- 
-- h_blank: This is the captured H bit from the last TRS symbol.
-- 
-- horz_position: This output represents the current horizontal position of the
-- video. It resets to zero at the end of each SAV and then increments every 
-- clock cycle.
-- 
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

use work.hdsdi_pkg.all;

entity hdsdi_rx_timing is
    port (
        clk:            in  std_logic;          -- clock input
        rst:            in  std_logic;          -- async reset input
        ln_in:          in  hd_vpos_type;       -- line number input
        vid_in:         in  hd_video_type;      -- either Y or C channel video input
        xyz:            in  std_logic;          -- input asserted during XYZ of TRS
        sav:            in  std_logic;          -- input asserted during SAV of TRS
        frame_start:    out std_logic;          -- asserted during h blank when ln = 1
        field:          out std_logic;          -- field indicator
        v_blank:        out std_logic;          -- asserted during vertical blanking interval
        h_blank:        out std_logic;          -- asserted during horizontal blanking interval
        horz_position:  out hd_hpos_type        -- 12-bit horizontal position
    );
end hdsdi_rx_timing;

architecture synth of hdsdi_rx_timing is

--
-- Signal declarations
--
signal f :          std_logic;                  -- F bit register
signal v :          std_logic;                  -- V bit register
signal h :          std_logic;                  -- H bit register
signal h_count :    hd_hpos_type;               -- horizontal position counter
signal first_line : hd_hpos_type;               -- value of line 1

begin

--
-- H, V, and F bit registers
--
process(clk, rst)
begin
    if rst = '1' then
        f <= '0';
        v <= '0';
        h <= '0';
    elsif clk'event and clk = '1' then
        if xyz = '1' then
            f <= vid_in(8);
            v <= vid_in(7);
            h <= vid_in(6);
        end if;
    end if;
end process;

field   <= f;
v_blank <= v;
h_blank <= h;


--
-- Horzontal position counter
--
process(clk, rst)
begin
    if rst = '1' then
        h_count <= (others => '0');
    elsif clk'event and clk = '1' then
        if sav = '1' then
            h_count <= (others => '0');
        else
            h_count <= h_count + 1;
        end if;
    end if;
end process;

horz_position <= h_count;

--
-- frame_start output logic
--
first_line <= (0 => '1', others => '0');
frame_start <= '1' when (ln_in = first_line) and (h = '1') else '0';

end synth;