hdsdi_encoder.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: hdsdi_encoder.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-12-09 14:55:19-07 $
-- /___/   /\    Date Created: May 28, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: hdsdi_encoder.vhd,rcs $
-- Revision 1.1  2004-12-09 14:55:19-07  jsnow
-- Cosmetic changes only.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
-- 
-- Description of module:
-- 
-- This module is the top-level module of the HD-SDI encoder. This module 
-- encodes 20-bits of data, 10-bits of chroma (C) and 10-bits of luma (Y), per 
-- clock cycle. There is a three clock cycle latency through the module.
-- 
-- This module  instances the smpte_encoder module twice, with one instance 
-- encoding the C channel and the other the Y channel. The two modules are cross
-- connected so that the results from one encoder affects the encoding of the
-- bits in the other encoder, as required by the HD-SDI encoding scheme.
--
-- The q output is a 20-bit encoded value. Note that this value must be
-- bit-swapped before it can be connected to the 20-bit input of the RocketIO
-- transmitter.
-- 
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

use work.hdsdi_pkg.all;

entity hdsdi_encoder is
    port (
        clk:        in  std_logic;      -- word rate clock (74.25 MHz)
        rst:        in  std_logic;      -- async reset
        ce:         in  std_logic;      -- clock enable
        nrzi:       in  std_logic;      -- 1 enables NRZ-to-NRZI conversion
        scram:      in  std_logic;      -- 1 enables SDI scrambler
        c:          in  hd_video_type;  -- C channel input data port
        y:          in  hd_video_type;  -- Y channel input data port
        q:          out hd_vid20_type); -- output data port
end hdsdi_encoder;

architecture synth of hdsdi_encoder is

component smpte_encoder is
    port (
        clk:        in  std_logic;      -- word rate clock (74.25 MHz)
        rst:        in  std_logic;      -- async reset
        ce:         in  std_logic;      -- clock enable
        nrzi:       in  std_logic;      -- 1 enables NRZ-to-NRZI conversion
        scram:      in  std_logic;      -- 1 enables SDI scrambler
        d:          in  hd_video_type;  -- input data port
        p_scram:    in                  -- previously scrambled data input
                        std_logic_vector(8 downto 0);
        p_nrzi:     in  std_logic;      -- MSB of previously converted NRZI word
        q:          out hd_video_type;  -- output data port
        i_scram:    out                 -- intermediate scrambled data output
                        std_logic_vector(8 downto 0);
        i_scram_q:  out                 -- registered intermediate scrambled data
                        std_logic_vector(8 downto 0);
        i_nrzi:     out std_logic);     -- intermediate nrzi data output
end component;

-- Internal signal definitions
signal c_in_reg :   hd_video_type;      -- C channel input register
signal y_in_reg :   hd_video_type;      -- Y channel input register
signal c_i_scram :                      -- C channel intermediate scrambled data
                    std_logic_vector(8 downto 0);
signal y_i_scram_q:                     -- Y channel intermediate scrambled data
                    std_logic_vector(8 downto 0);
signal c_i_nrzi:    std_logic;          -- C channel intermediate nrzi data
signal c_out :      hd_video_type;      -- output of C scrambler
signal y_out :      hd_video_type;      -- output of Y scrambler

begin

    --
    -- Instantiate encoder modules for C and Y channels
    --
    C_scram : smpte_encoder
        port map (
            clk         => clk,
            rst         => rst,
            ce          => ce,
            nrzi        => nrzi,
            scram       => scram,
            d           => c_in_reg,
            p_scram     => y_i_scram_q,
            p_nrzi      => y_out(9),
            q           => c_out,
            i_scram     => c_i_scram,
            i_scram_q   => open,
            i_nrzi      => c_i_nrzi);

    Y_scram : smpte_encoder
        port map (
            clk         => clk,
            rst         => rst,
            ce          => ce,
            nrzi        => nrzi,
            scram       => scram,
            d           => y_in_reg,
            p_scram     => c_i_scram,
            p_nrzi      => c_i_nrzi,
            q           => y_out,
            i_scram     => open,
            i_scram_q   => y_i_scram_q,
            i_nrzi      => open);

    --
    -- Input registers
    --
    process(clk, rst)
    begin
        if rst = '1' then
            c_in_reg <= (others => '0');
            y_in_reg <= (others => '0');
        elsif clk'event and clk = '1' then
            if ce = '1' then
                c_in_reg <= c;
                y_in_reg <= y;
            end if;
        end if;
    end process;

    --
    -- Output assignment
    --
    q <= (y_out & c_out);

end synth;