hdsdi_rx2.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

signal dec_bypass_mux : hd_vid20_type;      -- decoder bypass mux
signal ad_std :         hd_vidstd_type;     -- std output of autodetect module
signal ad_locked :      std_logic;          -- std_locked output of autodetect module
signal framer_c_out :   hd_video_type;      -- C channel out of framer
signal framer_y_out :   hd_video_type;      -- Y channel out of framer
signal c_ln_int :       hd_vpos_type;       -- internal version of c_ln
signal y_ln_int :       hd_vpos_type;       -- internal version of y_ln
signal ln_gen :         hd_vpos_type;       -- LN value generated by hdsdi_autodetect_ln
signal ln_valid :       std_logic;          -- ln_valid output of hdsdi_autodetect_ln
signal trs_int :        std_logic;          -- internal version of trs
signal eav_int :        std_logic;          -- internal version of eav
signal sav_int :        std_logic;          -- internal version of sav
signal xyz_int :        std_logic;          -- internal version of xyz
signal GND :            std_logic;          

component hdsdi_decoder
    port (
        clk:        in  std_logic;          -- word rate clock (74.25 MHz)
        rst:        in  std_logic;          -- async reset
        ce:         in  std_logic;          -- clock enable
        d:          in  hd_vid20_type;      -- input data port
        q:          out hd_vid20_type);     -- output data port
end component;

component hdsdi_framer_mult
    port (
        clk:        in  std_logic;          -- word rate clock (74.25 MHz)
        rst:        in  std_logic;          -- async reset
        ce:         in  std_logic;          -- clock enable
        d:          in  hd_vid20_type;      -- input data port
        frame_en:   in  std_logic;          -- enables resynch when high
        c:          out hd_video_type;      -- chroma channel output port
        y:          out hd_video_type;      -- luma channel output port
        trs:        out std_logic;          -- asserted when out reg contains a TRS symbol
        xyz:        out std_logic;          -- asserted when out reg contains XYZ of TRS
        eav:        out std_logic;          -- asserted when out reg contains XYZ of EAV
        sav:        out std_logic;          -- asserted when out reg contains XYZ of SAV
        trs_err:    out std_logic;          -- asserted if error detected in XYZ word
        nsp:        out std_logic);         -- new start position detected
end component;

component hdsdi_autodetect_ln
    port (
        clk:        in  std_logic;          -- clock input
        rst:        in  std_logic;          -- async reset input
        ce:         in  std_logic;          -- clock enable input
        vid_in:     in                      -- C or Y channel video input (bits 8:7 only)
                        std_logic_vector(8 downto 7);   
        eav:        in  std_logic;          -- XYZ word of EAV
        sav:        in  std_logic;          -- XYZ word of SAV
        reacquire:  in  std_logic;          -- force module to require new format
        std:        out hd_vidstd_type;     -- video format code
        locked:     out std_logic;          -- asserted when locked to video
        ln:         out hd_vpos_type;       -- line number output
        ln_valid:   out std_logic           -- asserted when ln is valid
    );
end component;

component hdsdi_rx_crc is
    port (
        clk:        in  std_logic;          -- receiver clock
        rst:        in  std_logic;          -- async reset
        ce:         in  std_logic;          -- clock enable
        c_video:    in  hd_video_type;      -- C channel video input port
        y_video:    in  hd_video_type;      -- Y channel video input port
        trs:        in  std_logic;          -- input asserted during all 4 words of TRS
        c_crc_err:  out std_logic;          -- C channel CRC error detected
        y_crc_err:  out std_logic;          -- Y channel CRC error detected
        c_line_num: out hd_vpos_type;       -- C channel received line number
        y_line_num: out hd_vpos_type);      -- Y channel received line number
end component;

begin

GND <= '0';

--
-- HD-SDI decoder module
--      
DEC : hdsdi_decoder 
    port map (
        clk         => clk,
        rst         => rst,
        ce          => ce,
        d           => rxdata,
        q           => dec_out
    );

--
-- Deocoder bypass MUX
--
dec_bypass_mux <= rxdata when dec_bypass = '1' else dec_out;

--
-- HD-SDI framer module
--
FRM : hdsdi_framer_mult 
    port map (
        clk         => clk,
        rst         => rst,
        ce          => ce,
        d           => dec_bypass_mux,
        frame_en    => frame_en,
        c           => framer_c_out,
        y           => framer_y_out,
        trs         => trs_int,
        xyz         => xyz_int,
        eav         => eav_int,
        sav         => sav_int,
        trs_err     => trs_err,
        nsp         => nsp   
    );

c_out <= framer_c_out;
y_out <= framer_y_out;
trs <= trs_int;
eav <= eav_int;
sav <= sav_int;
xyz <= xyz_int;


--
-- Receiver CRC checker
--
RX_CRC : hdsdi_rx_crc
    port map (
        clk         => clk,
        rst         => rst,
        ce          => ce,
        c_video     => framer_c_out,
        y_video     => framer_y_out,
        trs         => trs_int,
        c_crc_err   => c_crc_err,
        y_crc_err   => y_crc_err,
        c_line_num  => c_ln_int,
        y_line_num  => y_ln_int
    );


rx_ln <= y_ln_int;


--
-- Video format and line number generator
--
-- This module is optional and can be removed to reduce the design size. It
-- produces a code indicating which video format is being received. It also
-- generates line numbers that can be compared to the received line numbers.
--
AD : hdsdi_autodetect_ln
    port map (
        clk         => clk,
        rst         => rst,
        ce          => ce,
        vid_in      => framer_y_out(8 downto 7),
        eav         => eav_int,
        sav         => sav_int,
        reacquire   => GND,
        std         => ad_std,
        locked      => ad_locked,
        ln          => ln_gen,
        ln_valid    => ln_valid
    );

gen_ln <= ln_gen;
gen_ln_valid <= ln_valid;
std <= ad_std;
std_locked <= ad_locked;

end synth;