led_blink_counter.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: led_blink_counter.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-08-26 15:01:45-06 $
-- /___/   /\    Date Created: August 24, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: led_blink_counter.vhd,rcs $
-- Revision 1.0  2004-08-26 15:01:45-06  jsnow
-- Translated from Verilog.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
-- 
-- Description of module:
-- 
-- This clock divider divides the 33Mhz input clock down to get two different
-- LED blink frequencies, a fast and slow blink. The fast blink rate is about
-- 4Hz and the slow blink rate is about 1Hz.
-- 
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

library unisim; 
use unisim.vcomponents.all; 

entity led_blink_counter is
port (
    clk :           in  std_logic;          -- clock input
    slow :          out std_logic;          -- slow output clock
    fast :          out std_logic           -- fast output clock
);
end led_blink_counter;

architecture synth of led_blink_counter is

attribute init : string;
attribute init of srl1 : label is "0001";
attribute init of srl2 : label is "0001";
attribute init of srl3 : label is "0001";
attribute init of srl4 : label is "0001";
attribute init of srl5 : label is "0001";
attribute init of srl6 : label is "0001";

--
-- Internal signals
--
signal stage1 :     std_logic;                  -- stage 1 divider output
signal stage2 :     std_logic;                  -- stage 2 divider output
signal stage3 :     std_logic;                  -- stage 3 divider output
signal stage4 :     std_logic;                  -- stage 4 divider output
signal stage5 :     std_logic;                  -- stage 5 divider output
signal stage6 :     std_logic;                  -- stage 6 divider output
signal ce3 :        std_logic;                  -- stage 3 clock enable
signal ce4 :        std_logic;                  -- stage 4 clock enable
signal ce5 :        std_logic;                  -- stage 5 clock enable
signal ce6 :        std_logic;                  -- stage 6 clock enable
signal ce_fast :    std_logic;                  -- fast FF clock enable
signal fast_q :     std_logic;                  -- fast FF
signal mid_q :      std_logic;                  -- mid FF
signal slow_q :     std_logic;                  -- slow FF

begin

--
-- First stage divider (16)
--
srl1 : SRL16
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage1,
        A0  => '1',
        A1  => '1',
        A2  => '1',
        A3  => '1',
        CLK => clk,
        D   => stage1);
--
-- Second stage divider (16)
--   
srl2 : SRL16E 
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage2,
        A0  => '1',
        A1  => '1',
        A2  => '1',
        A3  => '1',
        CE  => stage1,
        CLK => clk,
        D   => stage2);
--
-- Third stage divider (16)
--   
ce3 <= stage1 and stage2;

srl3 : SRL16E 
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage3,
        A0  => '1',
        A1  => '1',
        A2  => '1',
        A3  => '1',
        CE  => ce3,
        CLK => clk,
        D   => stage3);
--
-- Fourth stage divider (16)
--   
ce4 <= stage1 and stage2 and stage3;

srl4 : SRL16E 
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage4,
        A0  => '1',
        A1  => '1',
        A2  => '1',
        A3  => '1',
        CE  => ce4,
        CLK => clk,
        D   => stage4);

--
-- Fifth stage divider (16)
--   
ce5 <= ce4 and stage4;

srl5 : SRL16E 
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage5,
        A0  => '1',
        A1  => '1',
        A2  => '1',
        A3  => '1',
        CE  => ce5,
        CLK => clk,
        D   => stage5);
--
-- Sixth stage divider (6)
--
ce6 <= ce4 and stage4 and stage5;

srl6 : SRL16E 
-- synthesis translate_off
    generic map (INIT => X"0001")
-- synthesis translate_on
    port map (
        Q   => stage6,
        A0  => '1',
        A1  => '0',
        A2  => '1',
        A3  => '0',
        CE  => ce6,
        CLK => clk,
        D   => stage6);


--
-- Final 3 divider flip-flops (fast, mid, slow)
--

ce_fast <= ce4 and stage4 and stage5 and stage6;

process(clk)
begin
    if clk'event and clk='1' then
        if ce_fast = '1' then
            fast_q <= not fast_q;
        end if;
    end if;
end process;

process(clk)
begin
    if clk'event and clk='1' then
        if ce_fast = '1' and fast_q = '1' then
            mid_q <= not mid_q;
        end if;
    end if;
end process;

process(clk)
begin
    if clk'event and clk='1' then
        if ce_fast = '1' and fast_q = '1' and mid_q = '1'then
            slow_q <= not slow_q;
        end if;
    end if;
end process;

fast <= fast_q;
slow <= slow_q;

end synth;