📄 hd_pass_demo.vhd
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rxdata: out hd_vid20_type; -- received data from RocketIO receiver
rxrecclk: out std_logic; -- clock recovered by RocketIO receiver
txp: out std_logic; -- serial output - true
txn: out std_logic -- serial output - complement
);
end component;
component hdsdi_rx2 is
port (
clk: in std_logic; -- receiver clock
rst: in std_logic; -- async reset
ce: in std_logic; -- clock enable
dec_bypass: in std_logic; -- high bypasses the HD-SDI decoder
frame_en: in std_logic; -- framer enable input
rxdata: in hd_vid20_type; -- input data bus
c_out: out hd_video_type; -- chroma channel data output
y_out: out hd_video_type; -- luma channel data output
nsp: out std_logic; -- new start position output
trs: out std_logic; -- asserted during TRS symbols
xyz: out std_logic; -- asserted during XYZ word of TRS symbols
eav: out std_logic; -- asserted during XYZ word of an EAV
sav: out std_logic; -- asserted during XYZ word of an SAV
trs_err: out std_logic; -- asserted during XYZ when error is detected
rx_ln: out hd_vpos_type; -- received Y channel line number
gen_ln: out hd_vpos_type; -- internally generated line number
gen_ln_valid: out std_logic; -- gen_ln is valid
c_crc_err: out std_logic; -- C channel CRC error
y_crc_err: out std_logic; -- Y channel CRC error
std: out hd_vidstd_type; -- 4-bit output code from video format detector
std_locked: out std_logic); -- indicates when std is valid
end component;
component hdsdi_rx_timing is
port (
clk: in std_logic; -- clock input
rst: in std_logic; -- async reset input
ln_in: in hd_vpos_type; -- line number input
vid_in: in hd_video_type; -- either Y or C channel video input
xyz: in std_logic; -- input asserted during XYZ of TRS
sav: in std_logic; -- input asserted during SAV of TRS
frame_start: out std_logic; -- asserted during h blank when ln = 1
field: out std_logic; -- field indicator
v_blank: out std_logic; -- asserted during vertical blanking interval
h_blank: out std_logic; -- asserted during horizontal blanking interval
horz_position: out hd_hpos_type -- 12-bit horizontal position
);
end component;
component rx_heartbeat is
port (
clk : in std_logic; -- clock input
xyz : in std_logic; -- indicates XYZ word of TRS
trs_err : in std_logic; -- indicates a TRS reception error
heartbeat : out std_logic -- heartbeat output
);
end component;
component multigenHD_logo is
port (
clk: in std_logic; -- video clock
rst: in std_logic; -- async reset
ce: in std_logic; -- clock enable
std: in std_logic_vector(2 downto 0); -- video standard select
pattern: in std_logic_vector(1 downto 0); -- selects pattern type (colorbars or checkfield)
user_opt: in std_logic_vector(1 downto 0); -- selects colorbars options
insert_logo: in std_logic; -- 1 = insert xilinx logo
y: out hd_video_type; -- Y channel output
c: out hd_video_type; -- C channel output
h_blank: out std_logic; -- horizontal blanking indicator
v_blank: out std_logic; -- vertical blanking indicator
field: out std_logic; -- field indicator
trs: out std_logic; -- asserted during 4 words of TRS
xyz: out std_logic; -- asserted during XYZ of TRS
line_num: out hd_vpos_type -- current vertical line number
);
end component;
component hdsdi_tx_path is
port (
clk: in std_logic; -- clock input
rst: in std_logic; -- async reset input
ce: in std_logic; -- clock enable input
c_in: in hd_video_type; -- chroma channel data input
y_in: in hd_video_type; -- luma channel data input
nrzi: in std_logic; -- high enables NRZ-to-NRZ conversion
scram: in std_logic; -- high enables SMPTE 292M scrambler
insert_crc: in std_logic; -- high enables generation & insertion of CRCs
force_crc_err: in std_logic; -- high forces CRC error to be generated
insert_ln: in std_logic; -- high enables line number insertion
ln: in hd_vpos_type; -- line numbers to be inserted
eav: in std_logic; -- input asserted during XYZ word of EAV symbol
sav: in std_logic; -- input asserted during XYZ word of SAV symbol
q: out hd_vid20_type -- encoded data output
);
end component;
component phasedetHD is
port (
vco: in std_logic;
refclk: in std_logic;
reset: in std_logic;
mkvcofaster: out std_logic;
mkvcoslower: out std_logic;
vco_tc: out std_logic;
refclk_tc: out std_logic);
end component;
-------------------------------------------------------------------------------
-- Signal definitions
--
-- Clock signals
signal clk_74_25M : std_logic; -- 74.25MHz clock after IOB
signal clk_74_17M : std_logic; -- 74.1758MHz clock after IOB
signal clk_hd_vcxo : std_logic; -- 74.1758MHz VCXO after IOB
signal clk_33M : std_logic; -- 33MHz clock after IOB
signal gclk_33M : std_logic; -- global 33MHz clock
-- Switch signals
signal dipsw : std_logic_vector(7 downto 0); -- DIP switches after IOBs
signal button1 : std_logic; -- pushbutton 1 after IOB
signal n_button1 : std_logic; -- inverse of button1
signal button2 : std_logic; -- pushbutton 2 after IOB
signal button3 : std_logic; -- pushbutton 3 after IOB
-- Internal LED control signals
signal mr_tx2_led_out : std_logic;
signal mr_tx1_led_out : std_logic;
signal mr_rx_led_out : std_logic;
signal asi_tx_led_out : std_logic;
signal sdi_rx_led_out : std_logic;
signal sdi_tx_led_out : std_logic;
signal mr_sync_led_out : std_logic;
signal mr_hd_led_out : std_logic;
signal mr_rate_led_out : std_logic;
signal sdi_sync_led_out : std_logic;
signal sdi_rate_led_out : std_logic;
signal mode_mr_led_out : std_logic;
signal mode_sdi_led_out : std_logic;
signal mode_asi_led_out : std_logic;
-- Signals for pass-through interface
signal rx_recclk : std_logic; -- recovered clock from RocketIO receiver
signal rx_usrclk : std_logic; -- rx_recclk after BUFG
signal rx_data : hd_vid20_type; -- data from RocketIO receiver
signal rx_nsp : std_logic; -- new start position from framer
signal rx_vid_y : hd_video_type; -- Y channel received video
signal rx_vid_c : hd_video_type; -- C channel received video
signal rx_ln : hd_vpos_type; -- rx line number
signal rx_new_ln : hd_vpos_type; -- line number form hdsdi_autodetect_ln
signal rx_new_ln_valid : std_logic; -- rx_new_ln is valid
signal rx_format : hd_vidstd_type; -- decoded video standard from hdsdi_autodetect_ln
signal rx_locked : std_logic; -- hdsdi_autodetect_ln is locked
signal clr_errs : std_logic; -- clear the error LED
signal crc_err_ff : std_logic; -- captures CRC errors
signal rx_y_crc_err : std_logic; -- Y channel CRC error from hdsdi_rx
signal rx_c_crc_err : std_logic; -- C channel CRC error from hdsdi_rx
signal rx_crc_err : std_logic; -- OR of Y and C CRC errors
signal rx_trs_err : std_logic; -- TRS error signal
signal rx_xyz : std_logic; -- xyz output of hdsdi_rx
signal rx_sav : std_logic; -- sav output of hdsdi_rx
signal rx_eav : std_logic; -- eav output of hdsdi_rx
signal rx_field : std_logic; -- field output from hdsdi_rx_timing
signal rx_v_blank : std_logic; -- v_blank output from hdsdi_rx_timing
signal rx_h_blank : std_logic; -- h_blank output from hdsdi_rx_timing
signal tx_data : hd_vid20_type; -- encoded data into RocketIO tx
signal insert_new_ln : std_logic; -- when 1, locally regenerated line numbers are inserted
-- when 0, original line numbers are passed through
signal insert_ln : std_logic; -- actual control input to hdsd_tx_path
signal insert_new_crc : std_logic; -- when 1, locally regenerated CRC values are inserted
-- when 0, original CRC values are passed through
signal heartbeat : std_logic; -- receiver heartbeat signal for LED
signal make_vcxo_faster : std_logic; -- VCXO control
signal make_vcxo_slower : std_logic; -- VCXO control
-- Signals for MR-Tx2 -- HD-SDI Tx driven from internal video pattern generator
signal tx2_usrclk : std_logic; -- global transmitter clock (BUFGMUX output)
signal tx2_refclksel : std_logic; -- RocketIO reference clock select
signal stdsel_reg : std_logic_vector(2 downto 0); -- input register for the standard select inputs
signal stdsel_syncreg : std_logic_vector(2 downto 0); -- synchronization register for std select inputs
signal tx2_vid_y : hd_video_type; -- video pat gen Y channel output
signal tx2_vid_c : hd_video_type; -- video pat gen C channel output
signal tx2_ln : hd_vpos_type; -- video pat gen line number output
signal tx2_xyz : std_logic; -- video pat gen XYZ word indicator
signal tx2_eav : std_logic; -- EAV signal into transmitter
signal tx2_sav : std_logic; -- SAV signal into transmitter
signal tx2_data : hd_vid20_type; -- encoded data to RocketIO transmitter
signal tx2_force_crc_err : std_logic; -- forces a CRC on Tx2 output
signal tx2_patsel : std_logic_vector(1 downto 0); -- pattern select for video pattern gen
signal tx2_insert_logo : std_logic; -- Xilinx logo enable for pattern gen
attribute IOSTANDARD : string;
attribute IOSTANDARD of HDXO1 : label is "LVDSEXT_25_DT";
attribute IOSTANDARD of HDXOM : label is "LVDSEXT_25_DT";
attribute IOSTANDARD of HDVCXO: label is "LVDSEXT_25_DT";
begin
--
-- Instantiate the startup block so that push_button1 drives the global reset
--
STARTV2 : STARTUP_VIRTEX2
port map (
CLK => '0',
GSR => n_button1,
GTS => '0');
-------------------------------------------------------------------------------
-- I/O Buffers
--
--
-- Push button switches
--
-- PB1 is global reset
-- PB2 resets the CRC error LED
-- PB3 forces CRC transmission errors out MR-Tx2
--
PB1 : IBUF_LVCMOS25
port map (
I => push_button1,
O => button1);
PB2 : IBUF_LVCMOS25
port map (
I => push_button2,
O => button2);
PB3 : IBUF_LVCMOS25
port map (
I => push_button3,
O => button3);
n_button1 <= not button1;
clr_errs <= not button2;
tx2_force_crc_err <= not button3;
--
-- DIP switches
--
SW0 : IBUF_LVCMOS25
port map (
I => dip_switches(0),
O => dipsw(0));
SW1 : IBUF_LVCMOS25
port map (
I => dip_switches(1),
O => dipsw(1));
SW2 : IBUF_LVCMOS25
port map (
I => dip_switches(2),
O => dipsw(2));
SW3 : IBUF_LVCMOS25
port map (
I => dip_switches(3),
O => dipsw(3));
SW4 : IBUF_LVCMOS25
port map (
I => dip_switches(4),
O => dipsw(4));
SW5 : IBUF_LVCMOS25
port map (
I => dip_switches(5),
O => dipsw(5));
SW6 : IBUF_LVCMOS25
port map (
I => dip_switches(6),
O => dipsw(6));
SW7 : IBUF_LVCMOS25
port map (
I => dip_switches(7),
O => dipsw(7));
tx2_refclksel <= dipsw(0);
--
-- LED Buffers
--
LED0 : OBUF_LVCMOS25
port map (
I => mr_tx2_led_out,
O => mr_tx2_led);
LED1 : OBUF_LVCMOS25
port map (
I => mr_tx1_led_out,
O => mr_tx1_led);
LED2 : OBUF_LVCMOS25
port map (
I => mr_rx_led_out,
O => mr_rx_led);
LED3 : OBUF_LVCMOS25
port map (
I => asi_tx_led_out,
O => asi_tx_led);
LED4 : OBUF_LVCMOS25
port map (
I => sdi_rx_led_out,
O => sdi_rx_led);
LED5 : OBUF_LVCMOS25
port map (
I => sdi_tx_led_out,
O => sdi_tx_led);
LED6 : OBUF_LVCMOS25
port map (
I => mr_sync_led_out,
O => mr_sync_led);
LED7 : OBUF_LVCMOS25
port map (
I => mr_hd_led_out,
O => mr_hd_led);
LED8 : OBUF_LVCMOS25
port map (
I => mr_rate_led_out,
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