hd_pass_demo.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: hd_pass_demo.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-12-09 15:14:08-07 $
-- /___/   /\    Date Created: August 25, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: hd_pass_demo.vhd,rcs $
-- Revision 1.2  2004-12-09 15:14:08-07  jsnow
-- XAPP577 version 1 release.
--
-- Revision 1.1  2004-08-26 16:20:30-06  jsnow
-- Cosmetic changes.
--
-- Revision 1.0  2004-08-26 15:07:22-06  jsnow
-- Translated from Verilog.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
-- 
-- Description of module:
-- 
-- This is the top level file for the SDV board HD-SDI pass-through demo.
-- 
-- This demo has one HD-SDI pass through interface. On this interface, the video
-- received through the MR-Rx HD-SDI receiver is retransmitted by the MR-Tx1
-- HD-SDI transmitter. A second HD-SDI transmitter, MR-Tx2, operates independently
-- and outputs video generated by an internal video pattern generator.
-- 
-- The pass-through interface checks all received video for CRC errors and
-- indicates the reception of a CRC error by flashing an LED on the SDV board.
-- The video stream retransmitted by the pass through interface can contain
-- either the original CRC and line number values, exactly as received by the
-- MR-Rx receiver or the CRC and line numbers can be regenerated by the interface.
-- In either case, the video is always decoded and framed by the MR-Rx receiver
-- and then re-encoded by the transmitter.
-- 
-- Due to the design of the SDV board, the pass-through interface can only operate
-- at one HD-SDI bit rate. This rate is dependent upon the frequency of the VCXO
-- on the board. Normally, this VCXO is 74.25/1.001 MHz.
-- 
-- The MR-Tx2 transmitter can, however, transmit at either HD-SDI bit rates since
-- it has access to reference frequencies for both bit rates.
-- 
-- The DIP switches on the SDV board perform the following functions in this demo:
-- 
-- SW0: Determines the bit rate of the MR-Tx2 transmitter
--  OFF: 1.485 Gbps
--  ON:  1.485/1.001 Gbps
-- 
-- SW[2:1]: Determine the video pattern transmitted by the MR-Tx2 transmitter
--  OFF OFF: RP-198 HD-SDI checkfield (pathological patterns)
--  OFF ON:  75% color bars
--  ON  OFF: SMPTE RP-219 color bars without Xilinx logo
--  ON  ON:  SMPTE RP-219 color bars with Xilinx logo inserted
--   
-- SW3: Controls whether the pass-through interface regenerates CRC
--  OFF: Received CRC values are passed through unmodified
--  ON:  New CRC values are calculated and replace the received CRCs
-- 
-- SW4: Controls whether the pass-through interface regenerates line numbers
--  OFF: Received line numbers are passed through unmodified
--  ON:  New line numbers are calculated and replace the received line numbers
-- 
-- SW[7:5]: Determine the video format output by the MR-Tx2 transmitter
--  OFF OFF OFF: SMPTE 296M - 720p   60 Hz or 59.94 Hz 
--  OFF OFF ON:  SMPTE 274M - 1080p  24 Hz or 23.98 Hz
--  OFF ON  OFF: SMPTE 274M - 1080p  25 Hz
--  OFF ON  ON:  SMPTE 274M - 1080p  30 Hz & 29.97 Hz
--  ON  OFF OFF: SMPTE 274M - 1080i  25 Hz
--  ON  OFF ON:  SMPTE 274M - 1080i  30 Hz & 29.97 Hz
--  ON  ON  OFF: SMPTE 274M - 1080sF 24 Hz & 23.98 Hz
--  ON  ON  ON:  SMPTE 295M - 1080i  25 Hz (1250 lines/frame)
-- 
-- The pushbutton switches on the SDV board have the following functions:
-- 
-- SW2: FPGA global reset
-- SW3: Clear the receiver CRC error LED
-- SW4: Force a CRC error in the video transmitted by MR-Tx2
-- 
-- Received CRC errors are indicated by the flashing of the leftmost LED
-- immediately below the pushbuttons. Once a single CRC error is detected, this
-- LED will continue to flash until cleared by pushing pushbutton SW3.
-- 
-- The LED above the MR-Rx BNC connector will flash when video is being received.
-- This LED indicates the detection of valid TRS symbols in the video and is used
-- as a "heartbeat" indication -- showing that data is being received.
-- 
-- Some video related signals are output to the J13 testpoints:
-- 
-- Pin 1: The recovered clock from the MR-Rx receiver (before jitter reduction)
-- Pin 2: CRC error (not latched) -- pulses every time a CRC error is detected
-- Pin 3: Field indicator from received video
-- Pin 4: Vertical blanking indicator from received video
-- Pin 5: Horizontal blanking indicator from received video
-- Pin 6: Stand-alone transmitter tx_usrclk
-- 
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

use work.hdsdi_pkg.all;

library unisim; 
use unisim.vcomponents.all; 

entity hd_pass_demo is
    port (
    -- Clock inputs    
        clk_74_25M_p:       in  std_logic;  -- 74.25MHz XO
        clk_74_25M_n:       in  std_logic;      
        clk_74_17M_p:       in  std_logic;  -- 74.1758MHz XO
        clk_74_17M_n:       in  std_logic;      
        clk_33M_in:         in  std_logic;  -- 33 MHz XO
        hd_vcxo_p:          in  std_logic;  -- 74.1758MHz VCXO
        hd_vcxo_n:          in  std_logic;          

    -- Clock control outputs
        hd_vcxo_up:         out  std_logic; -- makes HD-SDI VCXO faster
        hd_vcxo_down:       out  std_logic; -- makes HD-SDI VCXO slower
        ace_clk_en:         out  std_logic; -- 33MHz clock enable

    -- Switch inputs
        push_button1:       in  std_logic;        
        push_button2:       in  std_logic;      
        push_button3:       in  std_logic;      
        dip_switches:       in  std_logic_vector(7 downto 0);       

    -- HD-SDI serial inputs, outputs, and slew rate control
        mr_rx_rxp:          in  std_logic;  -- Rocket IO receiver input
        mr_rx_rxn:          in  std_logic;                    
        mr_tx1_txp:         out std_logic;  -- RocketIO transmitter output #1
        mr_tx1_txn:         out std_logic;
        mr_tx1_slewrate:    out std_logic;  -- slew rate control for cable driver
        mr_tx2_txp:         out std_logic;  -- Rocket IO transmitter output #2
        mr_tx2_txn:         out std_logic;         
        mr_tx2_slewrate:    out std_logic;  -- slew rate control for cable driver
        mr_rx2_rxp:         in  std_logic;  -- this RocketIO input pair is unused
        mr_rx2_rxn:         in  std_logic;      

    -- LEDs
        mr_tx2_led:         out std_logic;             
        mr_tx1_led:         out std_logic;             
        mr_rx_led:          out std_logic;              
        asi_tx_led:         out std_logic;             
        sdi_rx_led:         out std_logic;             
        sdi_tx_led:         out std_logic;             
        mr_sync_led:        out std_logic;            
        mr_hd_led:          out std_logic;              
        mr_rate_led:        out std_logic;            
        sdi_sync_led:       out std_logic;           
        sdi_rate_led:       out std_logic;           
        mode_mr_led:        out std_logic;            
        mode_sdi_led:       out std_logic;           
        mode_asi_led:       out std_logic;   
        
    -- Test outputs
        test_point:         out std_logic_vector(9 downto 0);            

    -- Outputs unused in this demo but required to be driven on the SDV Demo board
            
        sdi_vco_up:         out std_logic;
        sdi_vco_down:       out std_logic;
        vcxo_27M_up:        out std_logic;
        vcxo_27M_down:      out std_logic;
        vcxo_27M_sel:       out std_logic;
        ics660_s:           out std_logic_vector(3 downto 0);
        ics660_x1:          out std_logic;
        cypll_oe:           out std_logic;
        cypll_s2:           out std_logic;
        cypll_sclk:         out std_logic;
        cypll_sdat:         out std_logic;
        ics8745_clkout_p:   out std_logic;
        ics8745_clkout_n:   out std_logic;
        ics8745_sel:        out std_logic_vector(3 downto 0);
        ics8745_pll_sel:    out std_logic;
        ics8745_mr:         out std_logic;
        sdi_tx_dout_p:      out std_logic;
        sdi_tx_dout_n:      out std_logic;
        asi_tx_p:           out std_logic;
        asi_tx_n:           out std_logic;
        rs232_txd:          out std_logic;
        rs232_rts:          out std_logic
    );
end hd_pass_demo;

architecture synth of hd_pass_demo is

-------------------------------------------------------------------------------
-- Component definitions
--
component led_control is
    port (
        clk :               in  std_logic; 

        mr_tx2_on :         in  std_logic;
        mr_tx2_fast :       in  std_logic;
        mr_tx2_slow :       in  std_logic;
        mr_tx1_on :         in  std_logic;
        mr_tx1_fast :       in  std_logic;
        mr_tx1_slow :       in  std_logic;
        mr_rx_on :          in  std_logic;       
        mr_rx_fast :        in  std_logic;
        mr_rx_slow :        in  std_logic;
        asi_tx_on :         in  std_logic;      
        asi_tx_fast :       in  std_logic;
        asi_tx_slow :       in  std_logic;
        sdi_rx_on :         in  std_logic;      
        sdi_rx_fast :       in  std_logic;
        sdi_rx_slow :       in  std_logic;
        sdi_tx_on :         in  std_logic;      
        sdi_tx_fast :       in  std_logic;
        sdi_tx_slow :       in  std_logic;
        mr_sync_on :        in  std_logic; 
        mr_sync_fast :      in  std_logic;
        mr_sync_slow :      in  std_logic;
        mr_hd_on :          in  std_logic;       
        mr_hd_fast :        in  std_logic;
        mr_hd_slow :        in  std_logic;
        mr_rate_on :        in  std_logic; 
        mr_rate_fast :      in  std_logic;
        mr_rate_slow :      in  std_logic;
        sdi_sync_on :       in  std_logic;    
        sdi_sync_fast :     in  std_logic;
        sdi_sync_slow :     in  std_logic;
        sdi_rate_on :       in  std_logic;    
        sdi_rate_fast :     in  std_logic;
        sdi_rate_slow :     in  std_logic;
        mode_mr_on :        in  std_logic; 
        mode_mr_fast :      in  std_logic;
        mode_mr_slow :      in  std_logic;
        mode_sdi_on :       in  std_logic;    
        mode_sdi_fast :     in  std_logic;
        mode_sdi_slow :     in  std_logic;
        mode_asi_on :       in  std_logic;    
        mode_asi_fast :     in  std_logic;
        mode_asi_slow :     in  std_logic;

        mr_tx2_led :        out std_logic;     
        mr_tx1_led :        out std_logic;     
        mr_rx_led :         out std_logic;      
        asi_tx_led :        out std_logic;     
        sdi_rx_led :        out std_logic;     
        sdi_tx_led :        out std_logic;     
        mr_sync_led :       out std_logic;    
        mr_hd_led :         out std_logic;      
        mr_rate_led :       out std_logic;    
        sdi_sync_led :      out std_logic;   
        sdi_rate_led :      out std_logic;   
        mode_mr_led :       out std_logic;    
        mode_sdi_led :      out std_logic;   
        mode_asi_led :      out std_logic;

        clk_1Hz :           out std_logic
    );
end component;

component hdsdi_rio is
    port (
        brefclk:            in  std_logic;          -- BREFCLK
        brefclk2:           in  std_logic;          -- BREFCLK2
        refclk:             in  std_logic;          -- REFCLK
        refclk2:            in  std_logic;          -- REFCLK2
        refclk_sel:         in  std_logic;          -- selects between BREFCLK and BREFCLK2
        rst:                in  std_logic;          -- reset signal
        loopback_en:        in  std_logic;          -- loopback enable
        loopback_mode:      in  std_logic;          -- 0 is serial, 1 is parallel mode
        txinhibit:          in  std_logic;          -- inhibits transmitter when 1
        txdata:             in  hd_vid20_type;      -- data to be transmitted
        txusrclk:           in  std_logic;          -- transmitter usr clock
        txusrclk2:          in  std_logic;          -- transmitter usr clock 2
        rxusrclk:           in  std_logic;          -- receiver usr clock
        rxusrclk2:          in  std_logic;          -- receiver usr clock 2
        dcm_locked:         in  std_logic;          -- DCM for RXUSRCLKs is locked
        rxp:                in  std_logic;          -- serial input - true
        rxn:                in  std_logic;          -- serial input - complement
        rxdata:             out hd_vid20_type;      -- received data from RocketIO receiver
        rxrecclk:           out std_logic;          -- clock recovered by RocketIO receiver
        txp:                out std_logic;          -- serial output - true
        txn:                out std_logic           -- serial output - complement
    );                                              
end component;

component hdsdi_rio_refclk is
    port (
        brefclk:            in  std_logic;          -- BREFCLK
        brefclk2:           in  std_logic;          -- BREFCLK2
        refclk:             in  std_logic;          -- REFCLK
        refclk2:            in  std_logic;          -- REFCLK2
        refclk_sel:         in  std_logic;          -- selects between REFCLK and REFCLK2
        rst:                in  std_logic;          -- reset signal
        loopback_en:        in  std_logic;          -- loopback enable
        loopback_mode:      in  std_logic;          -- 0 is serial, 1 is parallel mode
        txinhibit:          in  std_logic;          -- inhibits transmitter when 1
        txdata:             in  hd_vid20_type;      -- data to be transmitted
        txusrclk:           in  std_logic;          -- transmitter usr clock
        txusrclk2:          in  std_logic;          -- transmitter usr clock 2
        rxusrclk:           in  std_logic;          -- receiver usr clock
        rxusrclk2:          in  std_logic;          -- receiver usr clock 2
        dcm_locked:         in  std_logic;          -- DCM for RXUSRCLKs is locked
        rxp:                in  std_logic;          -- serial input - true
        rxn:                in  std_logic;          -- serial input - complement