phasedethd.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: Leonard Dieguez
--  \   \        Filename: $RCSfile: phasedetHD.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-12-09 15:18:48-07 $
-- /___/   /\    Date Created: August 25, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: phasedetHD.vhd,rcs $
-- Revision 1.1  2004-12-09 15:18:48-07  jsnow
-- Cosmetic changes only.
--
-- Revision 1.0  2004-08-26 15:05:22-06  jsnow
-- Translated from Verilog.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
-- 
-- Description of module:
-- 
-- This module is the top level of the phase detector used in conjuction with an
-- external VCXO and loop filter to implement a PLL for jitter reducing the
-- recovered clock from the Rocket IO transceiver in a HD-SDI pass-through
-- application.
-- 
-------------------------------------------------------------------------------- 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

library unisim; 
use unisim.vcomponents.all; 

entity phasedetHD is
    port (
        vco:            in  std_logic;
        refclk:         in  std_logic;
        reset:          in  std_logic;
        mkvcofaster:    out std_logic;
        mkvcoslower:    out std_logic;
        vco_tc:         out std_logic;
        refclk_tc:      out std_logic);
end phasedetHD;

architecture synth of phasedetHD is

component pd_HD_VCXO is
    port (
        vco:            in  std_logic;
        refclk:         in  std_logic;
        reset:          in  std_logic;
        vcoisfast:      out std_logic;
        vcoisslow:      out std_logic;
        vco_tc:         out std_logic;
        refclk_tc:      out std_logic);
end component;

signal vcolocked :              std_logic;
signal vco_tc_int :             std_logic;
signal vcounlockedtrig :        std_logic;
signal vcolockedcntTC :         std_logic;
signal vcolockdet :             std_logic;
signal vcolockdetR :            std_logic;
signal vcolockedcnt :           std_logic_vector(15 downto 0);
signal GND16 :                  std_logic_vector(15 downto 0) := (others => '0');

begin

-------------------------------------------------------------------------------
--trigger pulse for "un-locked detection
--if the clocks are not rolling ie. in locked 
--condition vcolockdet and vcolockdetR should 
--always be the same.
--
process(refclk, reset)
begin
    if reset = '1' then
        vcolockdet  <= '0';
        vcolockdetR <= '0';
    elsif refclk'event and refclk='1' then
        vcolockdet  <= vco_tc_int;
        vcolockdetR <= vcolockdet;
    end if;
end process;

vcounlockedtrig <= vcolockdetR xor vcolockdet;

-------------------------------------------------------------------------------
--start a counter, reset if trig occurs, if the counter
--gets to 32K then assumed in locked condition.
--once in locked condition do not allow counter to count any more
--at this point try to lock to data.
--
process(refclk, reset)
begin
    if reset = '1' then
        vcolocked <= '0';
        vcolockedcnt <= GND16;
    elsif refclk'event and refclk='1' then
        if vcounlockedtrig = '1' and vcolockedcntTC = '0' then
            vcolocked <= '0';
            vcolockedcnt <= GND16;
        elsif vcolockedcntTC = '1' then
            vcolocked <= '1';
            vcolockedcnt <= vcolockedcnt;
        else
            vcolocked <= '0';
            vcolockedcnt <= vcolockedcnt + 1;
        end if;
    end if;
end process;

vcolockedcntTC <= vcolockedcnt(15);


-------------------------------------------------------------------------------
-- phase detector
pd : pd_HD_VCXO
    port map (
        vco         => vco,
        refclk      => refclk,
        reset       => reset,
        vcoisfast   => mkvcoslower,
        vcoisslow   => mkvcofaster,
        vco_tc      => vco_tc_int,
        refclk_tc   => refclk_tc);

vco_tc <= vco_tc_int;


end synth;