hdsdi_autodetect_ln.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

                elsif sav = '1' and first_act = '1' and f = '0' then
                    next_state <= LCK1;
                else
                    next_state <= LCK0;
                end if;

            when LCK1 => 
                if timeout = '1' then
                    next_state <= ERR;
                elsif sav = '1' then
                    next_state <= LCK2;
                else
                    next_state <= LCK1;
                end if;

            when LCK2 => 
                if timeout = '1' then
                    next_state <= ERR;
                elsif sav = '1' and v = '1' then
                    next_state <= LCK3;
                else
                    next_state <= LCK2;
                end if;

            when LCK3 => 
                if match = '1' then
                    next_state <= LCK0;
                else
                    next_state <= ERR;
                end if;

            when ERR => 
                if maxerrs = '1' then
                    next_state <= ACQ0;
                else
                    next_state <= LCK0;
                end if;

            when others => 
                next_state <= ACQ0;
        end case;
    end process;

    process(current_state, sav, first_act, match)
    begin
        en_wcnt         <= '0';
        en_lcnt         <= '0';
        clr_wcnt        <= '0';
        clr_lcnt        <= '0';
        set_locked      <= '0';
        clr_locked      <= '0';
        clr_errcnt      <= '0';
        inc_errcnt      <= '0';
        clr_loops       <= '0';
        inc_loops       <= '0';
        ld_std          <= '0';
        compare_sel     <= '0';

        case current_state is
            when ACQ0 => 
                clr_errcnt <= '1';
                clr_locked <= '1';
                clr_wcnt <= '1';
                clr_lcnt <= '1';

            when ACQ1 => 
                en_wcnt <= '1';
                en_lcnt <= '1';

            when ACQ2 => 
                en_lcnt <= '1';

            when ACQ3 => 
                clr_loops <= '1';

            when ACQ4 => 
                inc_loops <= '1';
                ld_std <= '1';
                if match = '1' then
                    clr_wcnt <= '1';
                end if;

            when LCK0 => 
                set_locked <= '1';
                en_wcnt <= '1';
                clr_lcnt <= '1';
                compare_sel <= '1';
                if sav = '1' then
                    clr_wcnt <= '1';
                end if;

            when LCK1 => 
                en_wcnt <= '1';
                en_lcnt <= '1';
                compare_sel <= '1';

            when LCK2 => 
                en_lcnt <= '1';
                compare_sel <= '1';

            when LCK3 => 
                compare_sel <= '1';
                clr_wcnt <= '1';
                if match = '1' then
                    clr_errcnt <= '1';
                end if;

            when ERR => 
                inc_errcnt <= '1';
                clr_wcnt <= '1';
                compare_sel <= '1';

            when others =>
                null; 
        end case;   
    end process;

    --
    -- Reset logic
    --
    -- The reset signal is maintained to the logic in this module for a few
    -- clock cycles after the global reset signal is removed.
    --
    reset <= rst or not reset_delay(7);

    process(clk, rst)
    begin
        if rst = '1' then
            reset_delay <= (others => '0');
        elsif clk'event and clk = '1' then
            reset_delay <= (reset_delay(6 downto 0) & '1');
        end if;
    end process;


    --
    -- ln generator
    --
    -- This code implements the line number generator. The line number generator
    -- is a counter that increments on the XYZ word of each EAV. It is initialized
    -- on the first active line of either  field. The initial value depends on
    -- the current standard and the field bit. The counter wraps back to zero when 
    -- it reaches the maximum line count for the current standard.
    --
    process(clk, rst)
    begin
        if rst = '1' then
            std_reg <= (others => '0');
        elsif clk'event and clk = '1' then
            if ce = '1' then
                if set_locked = '1' then
                    std_reg <= std_int;
                end if;
            end if;
        end if;
    end process;

    ln_load <= last_v and not v;

    process(clk, rst)
    begin
        if rst = '1' then
            ln_valid_q <= '0';
        elsif clk'event and clk = '1' then
            if ce = '1' then
                if locked_q = '0' then
                    ln_valid_q <= '0';
                elsif eav = '1' and ln_load = '1' then
                    ln_valid_q <= '1';
                end if;
            end if;
        end if;
    end process;

    ln_valid <= ln_valid_q;

    process(std_reg, f)
    begin
        case std_reg is
            when HD_FMT_1035i_30 =>
                if f = '0' then
                    ln_init <= std_logic_vector(TO_UNSIGNED(41,  HD_VCNT_WIDTH));
                else
                    ln_init <= std_logic_vector(TO_UNSIGNED(603,  HD_VCNT_WIDTH));
                end if;

            when HD_FMT_1080i_25b =>
                if f = '0' then
                    ln_init <= std_logic_vector(TO_UNSIGNED(81,  HD_VCNT_WIDTH));
                else
                    ln_init <= std_logic_vector(TO_UNSIGNED(706,  HD_VCNT_WIDTH));
                end if;

            when HD_FMT_1080i_30 =>
                if f = '0' then
                    ln_init <= std_logic_vector(TO_UNSIGNED(21,  HD_VCNT_WIDTH));
                else
                    ln_init <= std_logic_vector(TO_UNSIGNED(584,  HD_VCNT_WIDTH));
                end if;

            when HD_FMT_1080i_25 =>
                if f = '0' then
                    ln_init <= std_logic_vector(TO_UNSIGNED(21,  HD_VCNT_WIDTH));
                else
                    ln_init <= std_logic_vector(TO_UNSIGNED(584,  HD_VCNT_WIDTH));
                end if;

             when HD_FMT_1080p_30 => 
                 ln_init <= std_logic_vector(TO_UNSIGNED(42,  HD_VCNT_WIDTH));
                
             when HD_FMT_1080p_25 => 
                 ln_init <= std_logic_vector(TO_UNSIGNED(42,  HD_VCNT_WIDTH));
                
             when HD_FMT_1080p_24 => 
                 ln_init <= std_logic_vector(TO_UNSIGNED(42,  HD_VCNT_WIDTH));
                
             when HD_FMT_720p_60 => 
                 ln_init <= std_logic_vector(TO_UNSIGNED(26,  HD_VCNT_WIDTH));
                
            when HD_FMT_1080sF_24 =>
                if f = '0' then
                    ln_init <= std_logic_vector(TO_UNSIGNED(21,  HD_VCNT_WIDTH));
                else
                    ln_init <= std_logic_vector(TO_UNSIGNED(584,  HD_VCNT_WIDTH));
                end if;

             when HD_FMT_720p_50 => 
                 ln_init <= std_logic_vector(TO_UNSIGNED(26,  HD_VCNT_WIDTH));

            when others => 
                 ln_init <= std_logic_vector(TO_UNSIGNED(21,  HD_VCNT_WIDTH));

        end case;   
    end process;

    process(std_reg)
    begin
        case std_reg is
            when HD_FMT_1035i_30 => 
                ln_max <= std_logic_vector(TO_UNSIGNED(1125, HD_VCNT_WIDTH));

            when HD_FMT_1080i_25b => 
                ln_max <= std_logic_vector(TO_UNSIGNED(1250, HD_VCNT_WIDTH));

            when HD_FMT_1080i_30 => 
                ln_max <= std_logic_vector(TO_UNSIGNED(1125, HD_VCNT_WIDTH));

            when HD_FMT_1080i_25 => 
                ln_max <= std_logic_vector(TO_UNSIGNED(1125, HD_VCNT_WIDTH));

            when HD_FMT_1080p_30 => 
                ln_max <= std_logic_vector(TO_UNSIGNED(1125, HD_VCNT_WIDTH));

            when HD_FMT_1080p_25 => 
                ln_max <= std_logic_vector(TO_UNSIGNED(1125, HD_VCNT_WIDTH));

            when HD_FMT_1080p_24 => 
                ln_max <= std_logic_vector(TO_UNSIGNED(1125, HD_VCNT_WIDTH));

            when HD_FMT_720p_60 => 
                ln_max <= std_logic_vector(TO_UNSIGNED(750, HD_VCNT_WIDTH));

            when HD_FMT_1080sF_24 => 
                ln_max <= std_logic_vector(TO_UNSIGNED(1125, HD_VCNT_WIDTH));

            when HD_FMT_720p_50 => 
                ln_max <= std_logic_vector(TO_UNSIGNED(750, HD_VCNT_WIDTH));
         
            when others => 
                ln_max <= std_logic_vector(TO_UNSIGNED(1125, HD_VCNT_WIDTH));
                
        end case;
    end process;

    ln_tc <= '1' when ln_counter = ln_max else '0';

    process(clk, rst)
    begin
        if rst = '1' then
            ln_counter <= (0 => '1', others => '0');
        elsif clk'event and clk = '1' then
            if ce = '1' then
                if eav = '1' then
                    if ln_load = '1' then
                        ln_counter <= ln_init;
                    elsif ln_tc = '1' then
                        ln_counter <= (0 => '1', others => '0');
                    else
                        ln_counter <= ln_counter + 1;
                    end if;
                end if;
            end if;
        end if;
    end process;

    ln <= ln_counter;

end synth;