📄 hdsdi_framer_mult.vhd
字号:
--------------------------------------------------------------------------------
-- Copyright (c) 2004 Xilinx, Inc.
-- All Rights Reserved
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
-- \ \ Filename: $RCSfile: hdsdi_framer_mult.vhd,rcs $
-- / / Date Last Modified: $Date: 2006-01-05 07:59:29-07 $
-- /___/ /\ Date Created: May 28, 2004
-- \ \ / \
-- \___\/\___\
--
--
-- Revision History:
-- $Log: hdsdi_framer_mult.vhd,rcs $
-- Revision 1.2 2006-01-05 07:59:29-07 jsnow
-- Modified TRS detection to prevent false detection of TRS.
--
-- Revision 1.1 2004-12-09 14:48:05-07 jsnow
-- Cosmetic changes only.
--
--------------------------------------------------------------------------------
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE.
--
--------------------------------------------------------------------------------
-- Description of module:
--
-- SMPTE 292M-1998 HD-SDI is a standard for transmitting high-definition digital
-- video over a serial link. This module is exactly the same as the normal
-- hdsdi_framer module except that the barrel shifter is made from six
-- MULT18X18 blocks plus a little bit of decoding logic. This can reduce the
-- amount of fabric used by the framer if the multiplier blocks are available.
-- This framer uses 94 fewer 4-input LUTs than the standard framer, at the cost
-- of 6 MULT18X18 blocks.
--
-- This module accepts 20-bit parallel "unframed" data words from the HD-SDI
-- descrambler module and examines the bit stream for the 30-bit TRS pramble.
-- Once a TRS is found, the framer then knows the bit boundary of all subsequent
-- 10-bit characters in the bit stream and uses this offset to generate two 10-
-- bit parallel data words on its output every clock cycle.
--
-- The module has the following control inputs:
--
-- ce: The clock enable input controls loading of all registers in the module.
-- It must be asserted whenever a new 10-bit word is to be loaded into the
-- module. By providing a clock enable, this module can use a clock that is
-- running at the bit rate of the SDI bit stream if ce is asserted once every
-- ten clock cycles.
--
-- frame_en: This input controls whether the framer rsynchronize to new
-- character offsets when out-of-phase TRS symbols are detected. When this input
-- is high, out-of-phase TRS symbols will cause the framer to resynchronize.
--
-- The module generates the following outputs:
--
-- q: This 20-bit output port contains the properly framed data word.
--
-- trs: (timing reference signal) This output is asserted when the q output
-- register holds any of the four words of a TRS.
--
-- xyz: This output is asserted when the XYZ word of a TRS is output.
--
-- eav: This output is asserted when the XYZ word of an EAV is output.
--
-- sav: This output is asserted when the XYZ word of an SAV is output.
--
-- trs_err: This output is asserted during the XYZ word if an error is detected.
--
-- nsp: (new start position) If frame_en is low and a TRS is detected that does
-- not match the current character offset, this signal will be asserted high.
-- The nsp signal will remain asserted until the offset error has been
-- corrected.
--
-- There are normally three ways to use the frame_en input:
--
-- frame_en tied high: When frame_en is tied high, the framer will resynchronize
-- on every TRS detected.
--
-- frame_en tied to nsp: When in this mode, the framer implements TRS filtering.
-- If a TRS is detected that is out of phase with the existing character offset,
-- nsp will be asserted, but the framer will not resynchronize. If the next TRS
-- received is in phase with the current character offset, nsp will go low and
-- the will not resynchronize. If the next TRS arrives out of phase with the
-- current character offset, then the new character offset will be loaded and
-- nsp will be deasserted. Single erroneous TRS are ignored in this mode, but
-- if they persist, the decoder will adjust.
--
-- frame_en tied low: The automatic framing function is disabled when frame_en
-- is tied low. If data is being sent across the interface that does not comply
-- with the SDI standard and may contain data that looks like TRS symbols, the
-- framing function can be disabled in this manner.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.hdsdi_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity hdsdi_framer_mult is
port (
clk: in std_logic; -- word rate clock (74.25 MHz)
rst: in std_logic; -- async reset
ce: in std_logic; -- clock enable
d: in hd_vid20_type; -- input data port
frame_en: in std_logic; -- enables resynch when high
c: out hd_video_type; -- chroma channel output port
y: out hd_video_type; -- luma channel output port
trs: out std_logic; -- asserted when out reg contains a TRS symbol
xyz: out std_logic; -- asserted when out reg contains XYZ of TRS
eav: out std_logic; -- asserted when out reg contains XYZ of EAV
sav: out std_logic; -- asserted when out reg contains XYZ of SAV
trs_err: out std_logic; -- asserted if error detected in XYZ word
nsp: out std_logic); -- new start position detected
end hdsdi_framer_mult;
architecture synth of hdsdi_framer_mult is
-- Internal signal definitions
signal in_reg : hd_vid20_type; -- input register
signal dly_reg : hd_vid20_type; -- pipeline delay register
signal dly_reg2 : hd_vid20_type; -- pipeline delay register
signal offset_reg : -- offset register
std_logic_vector(4 downto 0);
signal barrel_in : -- input register for the barrel shifter
std_logic_vector(38 downto 0);
signal trs_out : -- used to generate the trs output signal
std_logic_vector(3 downto 0);
signal in_0 : std_logic_vector(38 downto 0);
-- input vector for zeros detector
signal in_1 : std_logic_vector(38 downto 0);
-- input vector for ones detector
signal ones_in : std_logic_vector(19 downto 0);
-- ones detector result vector
signal zeros_in : std_logic_vector(19 downto 0);
-- zeros detector result vector
signal zeros_dly : std_logic_vector(19 downto 0);
-- zeros detector result vector delayed
signal trs_match : std_logic_vector(19 downto 0);
-- TRS detector result vector
signal trs_detected : std_logic; -- asserted when TRS symbol is detected
signal offset_val : -- calculated offset value to load into offset reg
std_logic_vector(4 downto 0);
signal barrel_out : hd_vid20_type; -- output of barrel shifter
signal new_offset : std_logic; -- mismatch between offset_val and offset_reg
signal bs_in : -- input vector to barrel shifter first level
std_logic_vector(53 downto 0);
signal sc_top : std_logic; -- shift code for top level barrel shifter MUX
signal sc_bot : -- shift code for bottom level barrel shifter MUX
std_logic_vector(11 downto 0);
signal bstop_a : -- output of barrel shifter top level MULT18X18 A
std_logic_vector(35 downto 0);
signal bstop_b : -- output of barrel shifter top level MULT18X18 B
std_logic_vector(35 downto 0);
signal bstop_c : -- output of barrel shifter top level MULT18X18 C
std_logic_vector(35 downto 0);
signal bstop_bin : -- shift code input to top level multipliers
std_logic_vector(17 downto 0);
signal bstop : -- output of the barrel shifter's top level MUX section
std_logic_vector(26 downto 0);
signal bsbot_a : -- output of barrel shifter bottom level MULT18X18 A
std_logic_vector(35 downto 0);
signal bsbot_b : -- output of barrel shifter bottom level MULT18X18 B
std_logic_vector(35 downto 0);
signal bsbot_c : -- output of barrel shifter bottom level MULT18X18 C
std_logic_vector(35 downto 0);
signal bsbotc_ain : -- A input vector for BS_BOT_C multiplier
std_logic_vector(17 downto 0);
signal bsbot_bin : -- shift code input to bottom level multipliers
std_logic_vector(17 downto 0);
signal c_int : hd_video_type; -- C channel output register
signal y_int : hd_video_type; -- Y channel output register
signal xyz_int : std_logic; -- XYZ output register
signal GND20 : -- 20-bit vector of zeros
std_logic_vector(19 downto 0);
begin
GND20 <= (others => '0');
--
-- input register
--
-- 20-bit wide input register captures the received data from the decoder
-- module every clock cycle.
--
process(clk, rst)
begin
if rst = '1' then
in_reg <= (others => '0');
elsif clk'event and clk = '1' then
if ce = '1' then
in_reg <= d;
end if;
end if;
end process;
--
-- delay register
--
-- 20-bit wide delay register loads from the output of the in_reg.
--
process(clk, rst)
begin
if rst = '1' then
dly_reg <= (others => '0');
elsif clk'event and clk = '1' then
if ce = '1' then
dly_reg <= in_reg;
end if;
end if;
end process;
--
-- delay register 2
--
-- 20-bit wide delay register loads from the output of the dly_reg.
--
process(clk, rst)
begin
if rst = '1' then
dly_reg2 <= (others => '0');
elsif clk'event and clk = '1' then
if ce = '1' then
dly_reg2 <= dly_reg;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- TRS detector and offset encoder
--
-- The TRS detector identifies the 60-bit TRS sequence consisting of 20 '1'
-- bits followed by 40 '0' bits. The first level of the TRS detector
-- consists of a ones detector and a zeros detector. The ones dectector
-- looks for a run of 20 consecutive ones in the in_1 vector. The in_1
-- vector is a 39-bit vector made up of the contents of dly_reg2 and the 19
-- LSBs of dly_reg. The zeros detector looks for a run of 20 consecutive '0'
-- bits in the in_0 vector. The in_0 vector is 39-bits wide and is made up
-- of in_reg and the 19 LSBs of the d input port. The output of the zeros
-- detector is stored in the zeros_dly register so that the zeros detector
-- can be used twice to find two consecutive runs of 20 zeros. The output of
-- the zeros detector (both zeros_in and zeros_dly) and the ones detector
-- (ones_in) are 20-bit vectors with a bit for each possible starting
-- position of the 20-bit run.
--
-- A vector called trs_match is created by ORing the ones_in, zeros_in, and
-- zeros_dly values together. The 20-bit trs_match vector will have a
-- single bit set indicating the starting position of a TRS if one is
-- present in the input vector. The trs_detected signal, asserted when a
-- TRS is detected, can then be created by ORing all of the bits of
-- trs_match together. And, the offset_val, which is a 4-bit binary value
-- indicating the starting position of the the TRS to the barrel shifter,
-- can be generated from the trs_match vector.
--
in_0 <= (d(18 downto 0) & in_reg);
in_1 <= (dly_reg(18 downto 0) & dly_reg2);
--
-- zeros detector
--
process(in_0)
begin
for l in 0 to 19 loop
zeros_in(l) <= not (in_0(l+19) or in_0(l+18) or in_0(l+17) or in_0(l+16) or
in_0(l+15) or in_0(l+14) or in_0(l+13) or in_0(l+12) or
in_0(l+11) or in_0(l+10) or in_0(l+ 9) or in_0(l+ 8) or
in_0(l+ 7) or in_0(l+ 6) or in_0(l+ 5) or in_0(l+ 4) or
in_0(l+ 3) or in_0(l+ 2) or in_0(l+ 1) or in_0(l+ 0));
end loop;
end process;
--
-- ones detector
--
process(in_1)
begin
for m in 0 to 19 loop
ones_in(m) <= in_1(m+19) and in_1(m+18) and in_1(m+17) and in_1(m+16) and
in_1(m+15) and in_1(m+14) and in_1(m+13) and in_1(m+12) and
in_1(m+11) and in_1(m+10) and in_1(m+ 9) and in_1(m+ 8) and
in_1(m+ 7) and in_1(m+ 6) and in_1(m+ 5) and in_1(m+ 4) and
in_1(m+ 3) and in_1(m+ 2) and in_1(m+ 1) and in_1(m+ 0);
end loop;
end process;
--
-- zeros delay register
--
process(clk, rst)
begin
if rst = '1' then
zeros_dly <= (others => '0');
elsif clk'event and clk = '1' then
zeros_dly <= zeros_in;
end if;
end process;
--
-- trs_match and trs_detected signals
--
trs_match <= zeros_in and zeros_dly and ones_in;
trs_detected <= '0' when trs_match = GND20 else '1';
--
-- The following assignments encode the trs_match_all vector into a binary
-- offset code.
--
offset_val(0) <= trs_match(1) or trs_match(3) or trs_match(5) or
trs_match(7) or trs_match(9) or trs_match(11) or
trs_match(13) or trs_match(15) or trs_match(17) or
trs_match(19);
offset_val(1) <= trs_match(2) or trs_match(3) or trs_match(6) or
trs_match(7) or trs_match(10) or trs_match(11) or
trs_match(14) or trs_match(15) or trs_match(18) or
trs_match(19);
offset_val(2) <= trs_match(4) or trs_match(5) or trs_match(6) or
trs_match(7) or trs_match(12) or trs_match(13) or
trs_match(14) or trs_match(15);
offset_val(3) <= trs_match(8) or trs_match(9) or trs_match(10) or
trs_match(11) or trs_match(12) or trs_match(13) or
trs_match(14) or trs_match(15);
offset_val(4) <= trs_match(16) or trs_match(17) or trs_match(18) or
trs_match(19);
--
-- offset_reg: barrel shifter offset register
--
-- The offset_reg loads the offset_val whenever trs_detected is
-- asserted and trs_error is not asserted and frame_en is asserted.
--
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -