led_control.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: led_control.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-12-09 14:59:12-07 $
-- /___/   /\    Date Created: May 25, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: led_control.vhd,rcs $
-- Revision 1.1  2004-12-09 14:59:12-07  jsnow
-- Cosmetic changes only.
--
-- Revision 1.0  2004-08-26 15:03:04-06  jsnow
-- Translated from Verilog.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
-- 
-- Description of module:
-- 
-- This module controls the LEDs on the SDV demo board.
-- 
-- For each LED there are three inputs. If the xxx_on input is asserted high, 
-- then the LED will be on constantly, regardless of the other inputs. If the 
-- xxx_on input is low and the xxx_fast input is high, the LED will blink at a 
-- rate of about 4Hz. If the xxx_on and xxx_fast inputs are both low and the 
-- xxx_slow input is high, the LED will blink at a rate of about 1Hz. If none of
-- the inputs are high, then the LED will be off.
-- 
-- The module currently assumes an input clock of 33MHz and contains a
-- divider circuit to divide this clock down to the blink frequencies. 
-- 
-- The module instances the output buffers for all the LEDs on the SDV demo 
-- board.
--------------------------------------------------------------------------------
  
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity led_control is
port (
    clk :               in  std_logic;          -- clock input

    mr_tx2_on :         in  std_logic;
    mr_tx2_fast :       in  std_logic;
    mr_tx2_slow :       in  std_logic;
    mr_tx1_on :         in  std_logic;
    mr_tx1_fast :       in  std_logic;
    mr_tx1_slow :       in  std_logic;
    mr_rx_on :          in  std_logic;       
    mr_rx_fast :        in  std_logic;
    mr_rx_slow :        in  std_logic;
    asi_tx_on :         in  std_logic;      
    asi_tx_fast :       in  std_logic;
    asi_tx_slow :       in  std_logic;
    sdi_rx_on :         in  std_logic;      
    sdi_rx_fast :       in  std_logic;
    sdi_rx_slow :       in  std_logic;
    sdi_tx_on :         in  std_logic;      
    sdi_tx_fast :       in  std_logic;
    sdi_tx_slow :       in  std_logic;
    mr_sync_on :        in  std_logic; 
    mr_sync_fast :      in  std_logic;
    mr_sync_slow :      in  std_logic;
    mr_hd_on :          in  std_logic;       
    mr_hd_fast :        in  std_logic;
    mr_hd_slow :        in  std_logic;
    mr_rate_on :        in  std_logic; 
    mr_rate_fast :      in  std_logic;
    mr_rate_slow :      in  std_logic;
    sdi_sync_on :       in  std_logic;    
    sdi_sync_fast :     in  std_logic;
    sdi_sync_slow :     in  std_logic;
    sdi_rate_on :       in  std_logic;    
    sdi_rate_fast :     in  std_logic;
    sdi_rate_slow :     in  std_logic;
    mode_mr_on :        in  std_logic; 
    mode_mr_fast :      in  std_logic;
    mode_mr_slow :      in  std_logic;
    mode_sdi_on :       in  std_logic;    
    mode_sdi_fast :     in  std_logic;
    mode_sdi_slow :     in  std_logic;
    mode_asi_on :       in  std_logic;    
    mode_asi_fast :     in  std_logic;
    mode_asi_slow :     in  std_logic;

    mr_tx2_led :        out std_logic;     
    mr_tx1_led :        out std_logic;     
    mr_rx_led :         out std_logic;      
    asi_tx_led :        out std_logic;     
    sdi_rx_led :        out std_logic;     
    sdi_tx_led :        out std_logic;     
    mr_sync_led :       out std_logic;    
    mr_hd_led :         out std_logic;      
    mr_rate_led :       out std_logic;    
    sdi_sync_led :      out std_logic;   
    sdi_rate_led :      out std_logic;   
    mode_mr_led :       out std_logic;    
    mode_sdi_led :      out std_logic;   
    mode_asi_led :      out std_logic;

    clk_1Hz :           out std_logic
);
end led_control;

architecture synth of led_control is

component led_blink_counter is
port (
    clk :           in  std_logic;          -- clock input
    slow :          out std_logic;          -- slow output clock
    fast :          out std_logic           -- fast output clock
);
end component;

--
-- Internal signals
--

signal fast_blink : std_logic;
signal slow_blink : std_logic;

begin

mr_tx2_led <= '0' when mr_tx2_on = '1' else
              fast_blink when mr_tx2_fast = '1' else
              slow_blink when mr_tx2_slow = '1' else
              '1';

mr_tx1_led <= '0' when mr_tx1_on = '1' else
              fast_blink when mr_tx1_fast = '1' else
              slow_blink when mr_tx1_slow = '1' else
              '1';

mr_rx_led <= '0' when mr_rx_on = '1' else
              fast_blink when mr_rx_fast = '1' else
              slow_blink when mr_rx_slow = '1' else
              '1';


asi_tx_led <= '0' when asi_tx_on = '1' else
              fast_blink when asi_tx_fast = '1' else
              slow_blink when asi_tx_slow = '1' else
              '1';

sdi_rx_led <= '0' when sdi_rx_on = '1' else
              fast_blink when sdi_rx_fast = '1' else
              slow_blink when sdi_rx_slow = '1' else
              '1';

sdi_tx_led <= '0' when sdi_tx_on = '1' else
              fast_blink when sdi_tx_fast = '1' else
              slow_blink when sdi_tx_slow = '1' else
              '1';

mr_sync_led <= '0' when mr_sync_on = '1' else
              fast_blink when mr_sync_fast = '1' else
              slow_blink when mr_sync_slow = '1' else
              '1';

mr_hd_led <= '0' when mr_hd_on = '1' else
              fast_blink when mr_hd_fast = '1' else
              slow_blink when mr_hd_slow = '1' else
              '1';

mr_rate_led <= '0' when mr_rate_on = '1' else
              fast_blink when mr_rate_fast = '1' else
              slow_blink when mr_rate_slow = '1' else
              '1';

sdi_sync_led <= '0' when sdi_sync_on = '1' else
              fast_blink when sdi_sync_fast = '1' else
              slow_blink when sdi_sync_slow = '1' else
              '1';

sdi_rate_led <= '0' when sdi_rate_on = '1' else
              fast_blink when sdi_rate_fast = '1' else
              slow_blink when sdi_rate_slow = '1' else
              '1';

mode_mr_led <= '0' when mode_mr_on = '1' else
              fast_blink when mode_mr_fast = '1' else
              slow_blink when mode_mr_slow = '1' else
              '1';

mode_sdi_led <= '0' when mode_sdi_on = '1' else
              fast_blink when mode_sdi_fast = '1' else
              slow_blink when mode_sdi_slow = '1' else
              '1';

mode_asi_led <= '0' when mode_asi_on = '1' else
              fast_blink when mode_asi_fast = '1' else
              slow_blink when mode_asi_slow = '1' else
              '1';

LEDDIV : led_blink_counter
    port map (
        clk     => clk,
        slow    => slow_blink,
        fast    => fast_blink
    );

clk_1Hz <= slow_blink;

end synth;