hdsdi_rio_refclk.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: hdsdi_rio_refclk.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-08-23 13:23:41-06 $
-- /___/   /\    Date Created: May 21, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: hdsdi_rio_refclk.vhd,rcs $
-- Revision 1.1  2004-08-23 13:23:41-06  jsnow
-- Comment changes only.
--
-- Revision 1.0  2004-05-21 15:41:07-06  jsnow
-- Initial Revision
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
-- 
-- Description of module:
-- 
-- This module instantiates a single RocketIO transceiver using the GT_CUSTOM
-- primitive.
-- 
-- The modules swaps the txdata input vector to account for the fact that the
-- RocketIO transmitter sends the MSB first, whereas HD-SDI requires that the
-- LSB to be sent first. It does the same for the rxdata vector from the Rocket
-- IO receiver.
-- 
-- The module also includes the necessary logic to properly reset the RocketIO
-- transceiver. The RocketIO module is kept in reset until several clock cycles
-- after the dcm_locked signal is negated.
-- 
-- Note that this module connects the REFCLK, REFCLK2, BREFCLK, and BREFCLK2 
-- clock pins. However, it set the REF_CLK_V_SEL attribute of the GT_CUSTOM 
-- primitive to 0 so that only the REFCLK and REFCLK2 reference clock inputs 
-- are active. To use the BREFCLK and BREFCLK2 inputs, you must set the 
-- REF_CLK_V_SEL attribute to 1.
-- 
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.hdsdi_pkg.all;

library unisim; 
use unisim.vcomponents.all; 

entity hdsdi_rio_refclk is
    port (
        brefclk:        in  std_logic;      -- BREFCLK
        brefclk2:       in  std_logic;      -- BREFCLK2
        refclk:         in  std_logic;      -- REFCLK
        refclk2:        in  std_logic;      -- REFCLK2
        refclk_sel:     in  std_logic;      -- selects between BREFCLK and BREFCLK2
        rst:            in  std_logic;      -- reset signal
        loopback_en:    in  std_logic;      -- loopback enable
        loopback_mode:  in  std_logic;      -- 0 is serial, 1 is parallel mode
        txinhibit:      in  std_logic;      -- inhibits transmitter when 1
        txdata:         in  hd_vid20_type;  -- data to be transmitted
        txusrclk:       in  std_logic;      -- transmitter usr clock
        txusrclk2:      in  std_logic;      -- transmitter usr clock 2
        rxusrclk:       in  std_logic;      -- receiver usr clock
        rxusrclk2:      in  std_logic;      -- receiver usr clock 2
        dcm_locked:     in  std_logic;      -- DCM for RXUSRCLKs is locked
        rxp:            in  std_logic;      -- serial input - true
        rxn:            in  std_logic;      -- serial input - complement
        rxdata:         out hd_vid20_type;  -- received data from RocketIO receiver
        rxrecclk:       out std_logic;      -- clock recovered by RocketIO receiver
        txp:            out std_logic;      -- serial output - true
        txn:            out std_logic       -- serial output - complement
    );                             
end hdsdi_rio_refclk;

architecture synth of hdsdi_rio_refclk is


-- Internal wires
signal gt_rst :             std_logic;                      -- A delayed reset signal to satisfy the needs of the RocketIO
signal rst_x :              std_logic;                      -- gt_rst or reset
signal startup_counter:     std_logic_vector(2 downto 0);   -- used to generate gt_rst
signal txdata_swap:         std_logic_vector(19 downto 0);  -- data to be transmitted after bit swapping
signal recdata :            std_logic_vector(19 downto 0);  -- received data from RocketIO before bit swapping
signal loop_ctl :           std_logic_vector(1 downto 0);   -- loopback control signals
signal rxcharisk_float:     std_logic_vector(3 downto 2);   -- used to pad rxcharisk output to 4 bits
signal rxdata_float :       std_logic_vector(31 downto 16); -- used to pad rxdata output to 32 bits
signal rxrundisp_float:     std_logic_vector(3 downto 2);   -- used to pad rxrundisp output to 4 bits
signal gt_txchardispmode :  std_logic_vector(3 downto 0);
signal gt_txchardispval :   std_logic_vector(3 downto 0);
signal gt_txdata :          std_logic_vector(31 downto 0);
signal gt_rxcharisk :       std_logic_vector(3 downto 0);
signal gt_rxdata :          std_logic_vector(31 downto 0);
signal gt_rxrundisp :       std_logic_vector(3 downto 0);
signal GND1 :               std_logic;
signal GND :                std_logic_vector(3 downto 0);
signal GND2 :               std_logic_vector(15 downto 0);
signal VCC :                std_logic_vector(3 downto 0);

component GT_CUSTOM
    generic( 
        ALIGN_COMMA_MSB : boolean := FALSE;
        CHAN_BOND_LIMIT : integer := 16;
        CHAN_BOND_MODE : string := "OFF";
        CHAN_BOND_OFFSET : integer := 8;
        CHAN_BOND_ONE_SHOT : boolean := FALSE;
        CHAN_BOND_SEQ_1_1 : bit_vector := "00000000000";
        CHAN_BOND_SEQ_1_2 : bit_vector := "00000000000";
        CHAN_BOND_SEQ_1_3 : bit_vector := "00000000000";
        CHAN_BOND_SEQ_1_4 : bit_vector := "00000000000";
        CHAN_BOND_SEQ_2_1 : bit_vector := "00000000000";
        CHAN_BOND_SEQ_2_2 : bit_vector := "00000000000";
        CHAN_BOND_SEQ_2_3 : bit_vector := "00000000000";
        CHAN_BOND_SEQ_2_4 : bit_vector := "00000000000";
        CHAN_BOND_SEQ_2_USE : boolean := FALSE;
        CHAN_BOND_SEQ_LEN : integer := 1;
        CHAN_BOND_WAIT : integer := 8;
        CLK_COR_INSERT_IDLE_FLAG : boolean := FALSE;
        CLK_COR_KEEP_IDLE : boolean := FALSE;
        CLK_COR_REPEAT_WAIT : integer := 1;
        CLK_COR_SEQ_1_1 : bit_vector := "00000000000";
        CLK_COR_SEQ_1_2 : bit_vector := "00000000000";
        CLK_COR_SEQ_1_3 : bit_vector := "00000000000";
        CLK_COR_SEQ_1_4 : bit_vector := "00000000000";
        CLK_COR_SEQ_2_1 : bit_vector := "00000000000";
        CLK_COR_SEQ_2_2 : bit_vector := "00000000000";
        CLK_COR_SEQ_2_3 : bit_vector := "00000000000";
        CLK_COR_SEQ_2_4 : bit_vector := "00000000000";
        CLK_COR_SEQ_2_USE : boolean := FALSE;
        CLK_COR_SEQ_LEN : integer := 1;
        CLK_CORRECT_USE : boolean := TRUE;
        COMMA_10B_MASK : bit_vector := "1111111000";
        CRC_END_OF_PKT : string := "K29_7";
        CRC_FORMAT : string := "USER_MODE";
        CRC_START_OF_PKT : string := "K27_7";
        DEC_MCOMMA_DETECT : boolean := TRUE;
        DEC_PCOMMA_DETECT : boolean := TRUE;
        DEC_VALID_COMMA_ONLY : boolean := TRUE;
        MCOMMA_10B_VALUE : bit_vector := "1100000000";
        MCOMMA_DETECT : boolean := TRUE;
        PCOMMA_10B_VALUE : bit_vector := "0011111000";
        PCOMMA_DETECT : boolean := TRUE;
        REF_CLK_V_SEL : integer := 0;
        RX_BUFFER_USE : boolean := TRUE;
        RX_CRC_USE : boolean := FALSE;
        RX_DATA_WIDTH : integer := 2;
        RX_DECODE_USE : boolean := TRUE;
        RX_LOS_INVALID_INCR : integer := 1;
        RX_LOS_THRESHOLD : integer := 4;
        RX_LOSS_OF_SYNC_FSM : boolean := TRUE;
        SERDES_10B : boolean := FALSE;
        TERMINATION_IMP : integer := 50;
        TX_BUFFER_USE : boolean := TRUE;
        TX_CRC_FORCE_VALUE : bit_vector := "11010110";
        TX_CRC_USE : boolean := FALSE;
        TX_DATA_WIDTH : integer := 2;
        TX_DIFF_CTRL : integer := 500;
        TX_PREEMPHASIS : integer := 0
    );
    port (
        CHBONDI : in std_logic_vector (3 downto 0);
        CONFIGENABLE : in std_logic;
        CONFIGIN : in std_logic;
        ENMCOMMAALIGN : in std_logic;
        ENPCOMMAALIGN : in std_logic;
        ENCHANSYNC : in std_logic;
        LOOPBACK : in std_logic_vector (1 downto 0);
        POWERDOWN : in std_logic;
        REFCLK : in std_logic;
        REFCLK2 : in std_logic;
        REFCLKSEL : in std_logic;
        BREFCLK : in std_logic;
        BREFCLK2 : in std_logic;
        RXN : in std_logic;
        RXP : in std_logic;
        RXPOLARITY : in std_logic;
        RXRESET : in std_logic;
        RXUSRCLK : in std_logic;
        RXUSRCLK2 : in std_logic;
        TXBYPASS8B10B : in std_logic_vector (3 downto 0);
        TXCHARDISPMODE : in std_logic_vector (3 downto 0);
        TXCHARDISPVAL : in std_logic_vector (3 downto 0);
        TXCHARISK : in std_logic_vector (3 downto 0);
        TXDATA : in std_logic_vector (31 downto 0);
        TXFORCECRCERR : in std_logic;
        TXINHIBIT : in std_logic;
        TXPOLARITY : in std_logic;
        TXRESET : in std_logic;
        TXUSRCLK : in std_logic;
        TXUSRCLK2 : in std_logic;
        CHBONDDONE : out std_logic;
        CHBONDO : out std_logic_vector (3 downto 0);