hdsdi_decoder.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: hdsdi_decoder.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-12-09 14:46:08-07 $
-- /___/   /\    Date Created: May 28, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: hdsdi_decoder.vhd,rcs $
-- Revision 1.1  2004-12-09 14:46:08-07  jsnow
-- Cosmetic changes only.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
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--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
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--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
--
-- Description of module:
-- 
-- SMPTE 292M-1998 high-definition serial digital interface (HD-SDI) is a 
-- standard for transmitting high-definition digital video over a serial link.
-- 
-- HD-SDI specifies that the serial bit stream shall be encoded in two ways. 
-- First, a generator polynomial of x^9 + x^4 + 1 is used to generate a 
-- scrambled NRZ bit sequence. Next, a generator polynomial of x + 1 is used to 
-- produce the final polarity free NRZI sequence which is transmitted over the 
-- physical layer.
-- 
-- The decoder module described in this file sits at the receiving end of the
-- HD-SDI link and reverses the two encoding steps to extract the original data. 
-- First, the x + 1 generator polynomial is used to convert the bit stream from 
-- NRZI to NRZ. Next, the x^9 + x^4 + 1 generator polynomial is used to 
-- descramble the data.
-- 
-- This module works in parallel on 20-bits at a time. The module treats the 
-- data as a serial bit stream and isn't concerned about where the actual 
-- character boundaries are in the bit stream. 
-- 
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

use work.hdsdi_pkg.all;

entity hdsdi_decoder is
    port (
        clk:        in  std_logic;      -- word rate clock (74.25 MHz)
        rst:        in  std_logic;      -- async reset
        ce:         in  std_logic;      -- clock enable
        d:          in  hd_vid20_type;  -- input data port
        q:          out hd_vid20_type); -- output data port
end hdsdi_decoder;

architecture synth of hdsdi_decoder is

-- Internal signals
signal prev_d19 :   std_logic;      -- previous d[19] bit
signal prev_nrz :                   -- holds 9 MSB from NRZI-to-NRZ for use in next clock cycle
                    std_logic_vector(8 downto 0);
signal out_reg :    hd_vid20_type;  -- output register
signal desc_wide :                  -- concat of two input words used by descrambler
                    std_logic_vector(28 downto 0);
signal nrz :        hd_vid20_type;  -- output of NRZI-to-NRZ converter

begin
    --
    -- prev_d19 register
    --
    -- This register holds the MSB of the previous clock period's input port
    -- contents so that a 21-bit input vector is available to the NRZI-to-NRZ 
    -- converter.
    -- 
    process(clk, rst)
    begin
        if rst = '1' then
            prev_d19 <= '0';
        elsif clk'event and clk = '1' then
            if ce = '1' then
                prev_d19 <= d(19);
            end if;
        end if;
    end process;

    --
    -- NRZI-to-NRZ converter
    --
    -- The 20 XOR gates generated by this statement convert the 21-bit wide
    -- nrzi data to 20 bits of NRZ data. Each bit from the in_reg is XORed with
    -- the bit that preceeded it in the bit stream. The LSB of d is XORed with 
    -- the MSB of in_reg from the previous clock period that is held in the 
    -- prev_d19 register.
    --
    nrz <= d xor (d(18 downto 0) & prev_d19);

    --
    -- prev_nrz Input register of the descrambler
    --
    -- This register is a pipeline delay register which loads from the output of
    -- the NRZI-to-NRZ converter. It only holds the nine MSBs from the converter
    -- which get combined with 20-bits coming from the converter on the next 
    -- clock cycle to form a 29-bit wide input vector to the descrambler.
    --
    process(clk, rst)
    begin
        if rst = '1' then
            prev_nrz <= (others => '0');
        elsif clk'event and clk = '1' then
            if ce = '1' then
                prev_nrz <= nrz(19 downto 11);
            end if;
        end if;
    end process;

    desc_wide <= (nrz & prev_nrz);

    -- 
    -- Descrambler
    --
    -- A for loop is used to generate the HD-SDI x^9 + x^4 + 1 polynomial for 
    -- each of the 20-bits to be output using the 29-bit desc_wide input vector 
    -- that is made up of the contents of the prev_nrz register and the output 
    -- of the NRZI-to-NRZ converter.
    --
    process(clk, rst)
    begin
        if rst = '1' then
            out_reg <= (others => '0');
        elsif clk'event and clk = '1' then
            if ce = '1' then
                for i in 0 to 19 loop
                    out_reg(i) <= (desc_wide(i) xor desc_wide(i + 4)) xor 
                                   desc_wide(i + 9);
                end loop;
            end if;
        end if;
    end process;
            
    q <= out_reg;

end synth;