multigenhd_vert.vhd

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

-------------------------------------------------------------------------------- 
-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: multigenHD_vert.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2005-01-11 14:05:33-07 $
-- /___/   /\    Date Created: May 28, 2004 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: multigenHD_vert.vhd,rcs $
-- Revision 1.2  2005-01-11 14:05:33-07  jsnow
-- VHDL generics for INIT and SRVAL were only 32 bits instead of
-- the required 36 bits. This caused ModelSim errors.
--
-- Revision 1.1  2004-12-09 15:01:58-07  jsnow
-- Cosmetic changes only.
--
-------------------------------------------------------------------------------- 
--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
-------------------------------------------------------------------------------- 
-- This file contains the vertical sequencer for the HD video pattern generator.
-- A block RAM is used as a finite state machine, sequencing through the various
-- vertical sections of each video pattern. The module outputs a v_band code 
-- indicating which vertical portion of the video pattern should be displayed.      
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

use work.hdsdi_pkg.all;
use work.multigenHD_pkg.all;

library unisim; 
use unisim.vcomponents.all; 

entity multigenHD_vert is
    port (
        clk:            in  std_logic;                      -- video clock
        rst:            in  std_logic;                      -- async reset
        ce:             in  std_logic;                      -- clock enable
        std:            in  std_logic_vector(2 downto 0);   -- video standard select
        pattern:        in  std_logic_vector(1 downto 0);   -- selects pattern type (colorbars or checkfield)
        h_counter_lsb:  in  std_logic;                      -- LSB of horizontal counter
        v_inc:          in  std_logic;                      -- causes the vertical counter to increment
        v_band:         out vband_type;                     -- vertical band code output
        v:              out std_logic;                      -- vertical blanking indicator
        f:              out std_logic;                      -- field indicator
        first_line:     out std_logic;                      -- asserted during first active line
        y_ramp_inc_sel: out std_logic;                      -- controls Y-Ramp increment selection
        line_num:       out hd_vpos_type                    -- current vertical line number
    );
end multigenHD_vert;

architecture synth of multigenHD_vert is


-------------------------------------------------------------------------------
-- Signal definitions
--

signal vrom_addr :          std_logic_vector(8 downto 0);           -- VROM address
signal vrom_out :           std_logic_vector(31 downto 0);          -- VROM output
signal v_counter :          hd_vpos_type;                           -- vertical counter
signal v_next_evnt :        std_logic_vector(V_EVNT_MSB downto 0);  -- next vertical event
signal v_evnt_match :       std_logic;                              -- output of vertical event comparator
signal vrom_en :            std_logic;                              -- EN input to vertical ROM
signal v_region :           vrgn_type;                              -- current vertical region
signal v_band_rom :         vband_type;                             -- v_band for most patterns
signal v_band_75_rom :      vband_type;                             -- v_band for 75% color bars pattern
signal v_clr :              std_logic;                              -- clears the vertical counter
signal GND :                std_logic := '0';
signal VCC :                std_logic := '1';
signal GND4 :               std_logic_vector(3 downto 0) := "0000";
signal GND32 :              std_logic_vector(31 downto 0) := (others => '0');

attribute INIT : string;
attribute SRVAL : string;
attribute WRITE_MODE : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;

-- XST synthesis initialization code VROM
-- Created by multigenHD_romgen.v
-- Video format mapping:
--   000 =  SMPTE 295M - 1080i  25Hz (1250 lines/frame)
--   001 =  SMPTE 274M - 1080sF 24Hz & 23.98Hz         
--   002 =  SMPTE 274M - 1080i  30Hz & 29.97 Hz        
--   003 =  SMPTE 274M - 1080i  25Hz                   
--   004 =  SMPTE 274M - 1080p  30Hz & 29.97Hz         
--   005 =  SMPTE 274M - 1080p  25Hz                   
--   006 =  SMPTE 274M - 1080p  24Hz & 23.98Hz         
--   007 =  SMPTE 296M - 720p   60Hz & 59.94Hz         
attribute INIT of VROM : label is "00048FFFF";
attribute SRVAL of VROM : label is "00048FFFF";
attribute WRITE_MODE of VROM : label is "READ_FIRST";
attribute INITP_00 of VROM : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_01 of VROM : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of VROM : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of VROM : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of VROM : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of VROM : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of VROM : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of VROM : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_00 of VROM : label is "0018582800084E2702044D8602033CA5020237040201316302810A2200080A01";
attribute INIT_01 of VROM : label is "00089C4000089C4000589C5000189C2D02149BAC02138ACB0212852A02117F89";
attribute INIT_02 of VROM : label is "0038583800089C4000284E3702244D9502233CB4022237130221317200280A11";
attribute INIT_03 of VROM : label is "0008002000089C4000789C4000389C3D02349BBC02338ADB0232853A02317F99";
attribute INIT_04 of VROM : label is "0018582800084E2702040006020300050C064D860A052BC30A850A2200080A01";
attribute INIT_05 of VROM : label is "00089C4000089C4000589C5000189C2D0214000C0213000B0C169BAC0A1579E9";
attribute INIT_06 of VROM : label is "0038583800089C4000284E3702240015022300140C264D950A252BD200280A11";
attribute INIT_07 of VROM : label is "0008002000089C4000789C4000389C3D0234001C0233001B0C369BBC0A3579F9";
attribute INIT_08 of VROM : label is "001848E800084667020446060203352502022F84020129E3028102A200080281";
attribute INIT_09 of VROM : label is "00088CA000088CA000588CB000188C8D02148C6C02137B8B021275EA02117049";
attribute INIT_0A of VROM : label is "003848F800088CA000284677022446150223353402222F93022129F200280291";
attribute INIT_0B of VROM : label is "0008002000088CA000788CA000388C9D02348C7C02337B9B023275FA02317059";
attribute INIT_0C of VROM : label is "001848E80008466702040006020300050C0646060A0524430A8502A200080281";
attribute INIT_0D of VROM : label is "00088CA000088CA000588CB000188C8D0214000C0213000B0C168C6C0A156AA9";
attribute INIT_0E of VROM : label is "003848F800088CA00028467702240015022300140C2646150A25245200280291";
attribute INIT_0F of VROM : label is "0008002000088CA000788CA000388C9D0234001C0233001B0C368C7C0A356AB9";
attribute INIT_10 of VROM : label is "001848E800084667020446060203352502022F84020129E3028102A200080281";