hdsdi_tx_path.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------
// hdsdi_tx_path.v
//
// SMPTE 292M-1998 HD-SDI transmitter
//
//
//
//                  Author: John F. Snow
//                  Staff Applications Engineer
//
//                  Video Applications
//                  Advanced Products Group
//                  Xilinx, Inc.
//
//                  Copyright (c) 2003 Xilinx, Inc.
//                  All rights reserved
//
//                  RESTRICTED RIGHTS LEGEND
//
//      This software has not been published by the author, and 
//      has been disclosed to others for the purpose of enhancing 
//      and promoting design productivity in Xilinx products.
//
//      Therefore use, duplication or disclosure, now and in the 
//      future should give consideration to the productivity 
//      enhancements afforded the user of this code by the author's 
//      efforts.  Thank you for using our products !
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
// $Log: hdsdi_tx_path.v,rcs $
// Revision 1.0  2004-05-21 13:32:28-06  jsnow
// Initial revision
//
//
// Other modules instanced in this design:
//
//          hdsdi_encoder
//          hdsdi_crc
//          hdsdi_insert_crc
//          hdsdi_insert_ln
//
//------------------------------------------------------------------------------
/*
Description of module:

This contains most of the data path for the HD-SDI transmitter. It will insert
line numbers into the video stream (the line numbers are generated external to
this module). It will calculate the CRC values for each line and insert them
into the Y and C channels. Finally, it encodes the video and produces 20 bits
of encoded data ready for serialization.

There are several control inputs to this module:

insert_ln: a high enables the module to insert the line numbers from the ln
port into the video channels.

insert_crc: a high enables the module to insert the CRC values it calculates
into the video channels.

nrzi: a high enables the NRZ-to-NRZI portion of the SMPTE encoding algorithm

scram: a high enables the scrambling portion of the SMPTE encoding algorithm

force_crc_err: when high, this input forces the module to generate a bad CRC
value which will be inserted into only the C channel if insert_crc is also high.
The Y channel CRC value will not be affected.
 
The module also has the following timing and data inputs:

c_in, y_in: C and Y channel video inputs

ln: line number input port

eav: must be asserted when the XYZ word of an EAV is present on c_in and y_in

sav: must be asserted when the XYZ word of an SAV is present on c_in and y_in

The module does not contain any input or output registers. If timing can not be
met on the input side of the module, place pipeline delay registers on the
c_in, y_in, eav, and sav signals. The ln port may not need a pipeline delay
register if it remains asserted for several clock cycles after the EAV.

--------------------------------------------------------------------------------
*/

module hdsdi_tx_path (
    clk,                            // 74.25MHz TX USRCLK
    rst,                            // reset signal
    ce,                             // clock enable
    c_in,                           // chroma channel data input
    y_in,                           // luma channel data input
    nrzi,                           // high enables NRZ-to-NRZI converter
    scram,                          // high enables SMPTE 292M scramber
    insert_crc,                     // high enables generation & insertion of CRCs
    force_crc_err,                  // high forces CRC error to be generated
    insert_ln,                      // high enables line number insertion
    ln,                             // line numbers to be inserted
    eav,                            // input asserted during XYZ word of EAV symbol
    sav,                            // input asserted during XYZ word of SAV symbol
    q                               // encoded data output
);

//
// IO definitions   
//
input               clk;
input               rst;
input               ce;
input   [9:0]       c_in;
input   [9:0]       y_in;
input               nrzi;
input               scram;
input               insert_crc;
input               force_crc_err;
input               insert_ln;
input   [10:0]      ln;
input               eav;
input               sav;
output  [19:0]      q;

//
// Internal signals
//
wire    [17:0]      c_crc_calc;     // output of C channel CRC generator
wire    [17:0]      c_crc_out;      // CRC with forced CRC errors if force_crc_err asserted
wire    [17:0]      y_crc_out;      // output of Y channel CRC generator
wire    [9:0]       c_ln_out;       // output of C channel line number inserter
wire    [9:0]       y_ln_out;       // output of Y channel line number inserter
wire    [9:0]       c_crc_ins_out;  // C channel after CRC insertion
wire    [9:0]       y_crc_ins_out;  // Y channel after CRC insertion
reg                 crc_en;         // controls which words are included in CRC calculations
reg                 clr_crc;        // clears ssthe CRC calculators to start new calculation
reg     [3:0]       eav_dly;        // shift reg used to create video timing

//
// EAV delay register
//
// Generates timing control signals for line number insertion and CRC generation
// and insertion.
//
always @ (posedge clk or posedge rst)
    if (rst)
        eav_dly <= 0;
    else if (ce)
        eav_dly <= {eav_dly[2:0], eav};

//
// Instantiate the line number formatting and insertion module
//
hdsdi_insert_ln INS_LN (
    .insert_ln  (insert_ln),
    .ln_word0   (eav_dly[0]),
    .ln_word1   (eav_dly[1]),
    .c_in       (c_in),
    .y_in       (y_in),
    .ln         (ln),
    .c_out      (c_ln_out),
    .y_out      (y_ln_out));
        

//
// Generate timing control signals for the CRC calculators.
//
// The crc_en signal determines which words are included into the CRC 
// calculation. All words that enter the hdsdi_crc module when crc_en is high
// are included in the calculation. To meet the HD-SDI spec, the CRC calculation
// must being with the first word after the SAV and end after the second line
// number word after the EAV.
//
// The clr_crc signal clears the internal registers of the hdsdi_crc modules to
// cause a new CRC calculation to begin. The crc_en signal is asserted during
// the XYZ word of the SAV since the next word after the SAV XYZ word is the
// first word to be included into the new CRC calculation.
//
always @ (posedge clk or posedge rst)
    if (rst)
        crc_en <= 1'b0;
    else if (ce)
        begin
            if (sav)
                crc_en <= 1'b1;
            else if (eav_dly[1])
                crc_en <= 1'b0;
        end

always @ (posedge clk or posedge rst)
    if (rst)
        clr_crc <= 1'b0;
    else if (ce)
        clr_crc <= sav;

//
// Instantiate the CRC generators
//
hdsdi_crc C_CRC (
    .clk        (clk),
    .ce         (ce & crc_en),
    .rst        (rst),
    .clr        (clr_crc),
    .d          (c_ln_out),
    .crc_out    (c_crc_calc)
);

hdsdi_crc Y_CRC (
    .clk        (clk),
    .ce         (ce & crc_en),
    .rst        (rst),
    .clr        (clr_crc),
    .d          (y_ln_out),
    .crc_out    (y_crc_out)
);

//
// Force a C channel CRC error if force_crc_err is asserted by inverting the 
// LSB of the calculated C channel CRC value.
//
assign c_crc_out = {c_crc_calc[17:1], c_crc_calc[0] ^ force_crc_err};

//
// Insert the CRC values into the Y and C channels. The CRC values are inserted
// after the line number words after the EAV.
//
hdsdi_insert_crc CRC (
    .insert_crc (insert_crc),
    .crc_word0  (eav_dly[2]),
    .crc_word1  (eav_dly[3]),
    .y_in       (y_ln_out),
    .c_in       (c_ln_out),
    .y_crc      (y_crc_out),
    .c_crc      (c_crc_out),
    .y_out      (y_crc_ins_out),
    .c_out      (c_crc_ins_out));

//
// Instantiate the SMPTE 292M encoder
//

hdsdi_encoder ENC (
    .clk            (clk),
    .rst            (rst),
    .ce             (ce),
    .nrzi           (nrzi),
    .scram          (scram),
    .c              (c_crc_ins_out),
    .y              (y_crc_ins_out),
    .q              (q)
);

endmodule