📄 hdsdi_autodetect_ln.v
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//------------------------------------------------------------------------------
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
//------------------------------------------------------------------------------
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
// \ \ Filename: $RCSfile: hdsdi_autodetect_ln.v,rcs $
// / / Date Last Modified: $Date: 2005-06-23 13:07:51-06 $
// /___/ /\ Date Created: May 21, 2004
// \ \ / \
// \___\/\___\
//
//
// Revision History:
// $Log: hdsdi_autodetect_ln.v,rcs $
// Revision 1.4 2005-06-23 13:07:51-06 jsnow
// Code cleanup.
//
// Revision 1.3 2005-04-27 15:42:37-06 jsnow
// Added support for detecting 720p 50Hz.
//
// Revision 1.2 2004-08-23 13:06:49-06 jsnow
// Comment changes only.
//
// Revision 1.1 2004-05-21 13:10:46-06 jsnow
// Changed TRS timeout logic so the FSM will always timeout and negate the
// std_locked output if the input bit stream stops.
//
// Revision 1.0 2004-05-21 12:59:17-06 jsnow
// HD-SDI video format detection and line number generation
//------------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------
/*
This module will examine a HD video stream and detect the video standard. It
detects any of the 13 video standards currently supported by HD-SDI (SMPTE 260M,
SMPTE 295M, SMPTE 274M, and SMPTE 296M) plus the 1080sF video formats described
in SMPTE RP 211. This version of the module also supports the 720p 50Hz format.
The module counts words and lines to determine the video standard. It does not
depend on the inclusion of ANC packets identifying the video standard.
This module also produces a line number value indicating the current line number.
This line number value changes on the rising edge of clock following the XYZ
word of the EAV so that is valid for insertion into the LN field of an HD-SDI
stream.
The module requires as input only one of the channels of the video stream,
either Y or C. It also requires as input the decoded signals eav and sav
from the hdsdi_trs_decode module.
Normally, when the input video standard changes, this module will wait for
some number of video frames (determine by MAX_ERRCNT) before beginning the
process of identifying and locking to the new video format. This is to prevent
a few errors in the video from causing the module to lose lock. However, it also
increases the latency for the module to lock to a new standard when the input
video standard is deliberately changed. If some logic external to this module
knows that a deliberate input video standard change has been done, it can assert
this module's reacquire input for one clock cycle to force the module to
immediately begin the process of identifying and locking to the new video
standard.
The module generates the following outputs:
locked: Indicates when the module has locked to the incoming video standard. The
std and ln outputs are only valid when locked is a 1.
std: A 4-bit code indicating which video standard has been detected encoded
as follows:
0000: SMPTE 260M 1035i 30Hz
0001: SMPTE 295M 1080i 25Hz
0010: SMPTE 274M 1080i or 1080sF 30Hz
0011: SMPTE 274M 1080i or 1080sF 25Hz
0100: SMPTE 274M 1080p 30Hz
0101: SMPTE 274M 1080p 25Hz
0110: SMPTE 274M 1080p 24Hz
0111: SMPTE 296M 720p 60Hz
1000: SMPTE 274M 1080sF 24Hz
1001: SMPTE 296M 720p 50Hz
ln: An 11-bit line number code indicating the current line number. This code
changes on the rising edge of the clock when both xyz and eav are asserted. This
allows the ln code to be available just in time for encoding and insertion into
the two words that immediately follow the EAV. However, care must be taken to
insure that this path meets timing.
ln_valid: Asserted whenever the locked output is asserted and the line number
generator has started generating valid line numbers.
Note that the std code does not distinguish between the /1 and /M video
standards. So, the code 0010 can represent either a true 30Hz signal or 30Hz/M.
Also note that this module is unable to distinguish between the SMPTE 274M
1080i standards and the corresponding 1080sF standards since they both have
exactly the same video format in terms of number of lines per frame and words
per line.
*/
module hdsdi_autodetect_ln (
clk, // 74.25MHz or 74.25MHz/1.001 video clock input
rst, // async reset input
ce, // clock enable input
vid_in, // C or Y channel video input (only bits 8:7 are needed)
eav, // XYZ word of EAV
sav, // XYZ word of SAV
reacquire, // force module to decode & lock to new standard more quickly
std, // video standard code output
locked, // asserted when locked to video
ln, // line number output
ln_valid // asserted when ln is valid
);
//-----------------------------------------------------------------------------
// Parameter definitions
//
//
// This group of parameters defines the bit widths of various fields in the
// module.
//
parameter HCNT_WIDTH = 12; // Width of h_counter
parameter VCNT_WIDTH = 11; // Width of v_counter
localparam HCNT_MSB = HCNT_WIDTH - 1; // MS bit # of horizontal counter
localparam VCNT_MSB = VCNT_WIDTH - 1; // MS bit # of vertical counter
//
// Video standard parameters
//
parameter [3:0]
VSTD_260M = 0, // SMPTE 260M 1035i 30Hz
VSTD_295M = 1, // SMPTE 295M 1080i 25Hz
VSTD_274M_30i = 2, // SMPTE 274M 1080i 30Hz or 1080sF 30Hz
VSTD_274M_25i = 3, // SMPTE 274M 1080i 25Hz or 1080sF 25Hz
VSTD_274M_30p = 4, // SMPTE 274M 1080p 30Hz
VSTD_274M_25p = 5, // SMPTE 274M 1080p 25Hz
VSTD_274M_24p = 6, // SMPTE 274M 1080p 24Hz
VSTD_296M = 7, // SMPTE 296M 720p 60Hz
VSTD_RP211_24sF = 8, // SMPTE 274M 1080sF 24Hz
VSTD_296M_50 = 9; // SMPTE 296M 720p 50Hz
//
// The following parameter must be equal to the value of the last video format
// code in the table above. It is used to indicate the terminal count value of
// a counter used to search for valid video formats.
//
parameter LAST_VIDEO_FORMAT_CODE = VSTD_296M_50;
//
// State machine state assignments
//
localparam [3:0]
ACQ0 = 4'b0000,
ACQ1 = 4'b0001,
ACQ2 = 4'b0010,
ACQ3 = 4'b0011,
ACQ4 = 4'b0100,
LCK0 = 4'b0101,
LCK1 = 4'b0110,
LCK2 = 4'b0111,
LCK3 = 4'b1000,
ERR = 4'b1001;
//
// The MAX_ERRCNT parameter indicates the maximum number of consecutive frames
// that do not match the currently locked standard's parameters. If MAX_ERRCNT
// is exceeded the locked signal will be negated and the state machine will
// attempt to match the new video standard.
//
// Increasing the MAX_ERRCNT value improves the tolerance to errors in the
// video stream. However, it also increases the latency for the module to
// lock to a new standard when the input standard changes. If some external
// logic knows that the input video standard has changed, the state machine
// can be forced to reacquire the new standard more quickly by asserted the
// reacquire input for one clock cycle. This forces the state machine to start
// the process of identifying the new standard without having to wait for
// it to reach the MAX_ERRCNT number of errored frames before starting this
// process.
//
parameter [2:0]
MAX_ERRCNT = 3'b010; // max # of errored frames before unlocking
//-----------------------------------------------------------------------------
// Signal definitions
//
// IO definitions
input clk;
input rst;
input ce;
input [8:7] vid_in;
input eav;
input sav;
input reacquire;
output [3:0] std;
output locked;
output [VCNT_MSB:0] ln;
output ln_valid;
// Internal signals
reg [3:0] std_int; // internal video std output code
reg [HCNT_MSB:0] word_counter; // counts words per line
reg [HCNT_MSB:0] trs_to_counter; // TRS timeout counter
reg [VCNT_MSB:0] line_counter; // counts lines per field or frame
reg [3:0] current_state; // FSM current state
reg [3:0] next_state; // FSM next state
reg en_wcnt; // enables word counter
reg en_lcnt; // enables line counter
reg clr_wcnt; // clears word counter
reg clr_lcnt; // clears line counter
reg set_locked; // asserts the locked signal
reg clr_locked; // clears the locked signal
reg clr_errcnt; // clears the error counter
reg inc_errcnt; // increments the error counter
reg [3:0] loops; // iteration loop counter used by FSM
reg clr_loops; // clears loop counter
reg inc_loops; // increments loop counter
wire loops_tc; // asserted when loop counter equals 8
reg ld_std; // load std register
reg [2:0] errcnt; // error counter
wire maxerrs; // asserted when error counter reaches max allowed
wire match; // asserted when video standard match is found
wire match_words; // word counter matches video standard
wire match_lines; // line counter matches video standard
reg compare_sel; // controls comparator input MUX
wire [3:0] cmp_mux; // comparator input MUX
reg [HCNT_MSB:0] cmp_wcnt; // word count comparison value
reg [VCNT_MSB:0] cmp_lcnt; // line count comparison value
reg first_act; // asserted on first active line
reg last_v; // registered version of V bit from last line
wire v; // vertical blanking interval indicator (V bit)
wire f; // field indicator (F bit)
wire trs_timeout; // timed out waiting for TRS
wire first_timeout; // timed out waiting for first line
wire timeout; // timeout condition
reg locked_q; // locked flip-flop
reg ln_valid_q; // ln_valid flip-flop
reg [7:0] reset_delay; // delay register for reset signal
wire reset; // module reset
reg [VCNT_MSB:0] ln_counter; // counter for the ln generator
reg [VCNT_MSB:0] ln_init; // init value for the counter
reg [VCNT_MSB:0] ln_max; // max ln value for the current std
wire ln_tc; // asserted when ln_counter = ln_max
wire ln_load; // loads the ln_counter with ln_init
reg [3:0] std_reg; // holds internal copy of std for ln generation logic
reg reacquire_sync;
reg reacquire_q;
//
// reacquire synchronizer
//
// Since reacquire is a direct input to the FSM from parts unknown, make sure
// it is synchronous to the local clock before feeding it to the state machine.
//
always @ (posedge clk or posedge reset)
if (reset)
reacquire_q <= 1'b0;
else if (ce)
reacquire_q <= reacquire;
always @ (posedge clk or posedge reset)
if (reset)
reacquire_sync <= 1'b0;
else
reacquire_sync <= reacquire_q;
//
// word counter
//
// The word counter counts the number of words detected during a video line.
//
always @ (posedge clk or posedge reset)
if (reset)
word_counter <= 0;
else if (ce)
begin
if (clr_wcnt)
word_counter <= 0;
else if (en_wcnt)
word_counter <= word_counter + 1;
end
//
// trs timeout generator
//
// This timer will timeout if TRS symbols are not received on a periodic
// basis, causing the trs_timeout signal to be asserted.
//
always @ (posedge clk or posedge reset)
if (reset)
trs_to_counter <= 0;
else if (ce)
begin
if (eav | sav)
trs_to_counter <= 0;
else
trs_to_counter <= trs_to_counter + 1;
end
assign trs_timeout = &trs_to_counter;
//
// line counter
//
// The line counter counts the number of lines in a field or frame. The
// first_timeout signal will be asserted if the line counter reaches terminal
// count before the FSM clears the counter at the beginning of a new field or
// frame.
//
always @ (posedge clk or posedge reset)
if (reset)
line_counter <= 0;
else if (ce)
begin
if (clr_lcnt)
line_counter <= 0;
else if (en_lcnt & eav)
line_counter <= line_counter + 1;
end
assign first_timeout = &line_counter;
//
// The timeout signal will be asserted if either trs_timeout or first_timeout
// are asserted.
//
assign timeout = trs_timeout | first_timeout;
//
// error counter
//
// The error counter is incremented by the FSM when an error is detected. When
// the error counter reaches MAX_ERRCNT, the maxerrs signal will be asserted.
//
always @ (posedge clk or posedge reset)
if (reset)
errcnt <= 0;
else if (ce)
begin
if (clr_errcnt)
errcnt <= 0;
else if (inc_errcnt)
errcnt <= errcnt + 1;
end
assign maxerrs = errcnt == MAX_ERRCNT;
//
// loop counter
//
// The loop counter is a 4-bit binary up counter used by the FSM. It is used to
// cycle through the word & line count values for each of the supported video
// standards so that they can be compared to the values found in the input
// video stream. The loops_tc signal is asserted when the loop counter reaches
// its terminal count.
//
always @ (posedge clk or posedge reset)
if (reset)
loops <= 0;
else if (ce)
begin
if (clr_loops)
loops <= 0;
else if (inc_loops)
loops <= loops + 1;
end
assign loops_tc = loops == LAST_VIDEO_FORMAT_CODE;
//
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