led_blink_counter.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: led_blink_counter.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-10-15 09:08:01-06 $
// /___/   /\    Date Created: May 25, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: led_blink_counter.v,rcs $
// Revision 1.2  2004-10-15 09:08:01-06  jsnow
// Header update and comment changes.
//
// Revision 1.1  2004-06-07 12:39:31-06  jsnow
// Modified last divider stage from 8 to 4.
//
// Revision 1.0  2004-05-25 13:21:03-06  jsnow
// Initial revision
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

This clock divider divides the 33Mhz input clock down to get two different
LED blink frequencies, a fast and slow blink. The fast blink rate is about
4Hz and the slow blink rate is about 1Hz.

--------------------------------------------------------------------------------
*/

`timescale 1ns / 1ns

module led_blink_counter (
    input wire clk,                     // input clock
    output reg slow,                    // slow output clock
    output reg fast                     // fast output clock
);


wire                stage1;             // stage 1 divider output       
wire                stage2;             // stage 2 divider output
wire                stage3;             // stage 3 divider output
wire                stage4;             // stage 4 divider output
wire                stage5;             // stage 5 divider output
wire                stage6;             // stage 6 divider output
reg                 mid;                // mid FF
wire                ce_1to4;            // stage 5 clock enable
wire                ce_fast;            // fast FF clock enable

//
// First stage divider (16)
//
SRL16 srl1 (
    .Q   (stage1),
    .A0  (1'b1),
    .A1  (1'b1),
    .A2  (1'b1),
    .A3  (1'b1),
    .CLK (clk),
    .D   (stage1));

// synthesis translate_off
defparam srl1.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl1 is 1

//
// Second stage divider (16)
//   
SRL16E srl2 (
    .Q   (stage2),
    .A0  (1'b1),
    .A1  (1'b1),
    .A2  (1'b1),
    .A3  (1'b1),
    .CE  (stage1),
    .CLK (clk),
    .D   (stage2));

// synthesis translate_off
defparam srl2.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl2 is 1
               
//
// Third stage divider (16)
//   
SRL16E srl3 (
    .Q   (stage3),
    .A0  (1'b1),
    .A1  (1'b1),
    .A2  (1'b1),
    .A3  (1'b1),
    .CE  (stage1 & stage2),
    .CLK (clk),
    .D   (stage3));

// synthesis translate_off
defparam srl3.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl3 is 1

//
// Fourth stage divider (16)
//   
SRL16E srl4 (
    .Q   (stage4),
    .A0  (1'b1),
    .A1  (1'b1),
    .A2  (1'b1),
    .A3  (1'b1),
    .CE  (stage1 & stage2 & stage3),
    .CLK (clk),
    .D   (stage4));

// synthesis translate_off
defparam srl4.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl4 is 1

assign ce_1to4 = stage1 & stage2 & stage3 & stage4;

//
// Fifth stage divider (16)
//   
SRL16E srl5 (
    .Q   (stage5),
    .A0  (1'b1),
    .A1  (1'b1),
    .A2  (1'b1),
    .A3  (1'b1),
    .CE  (ce_1to4),
    .CLK (clk),
    .D   (stage5));

// synthesis translate_off
defparam srl5.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl5 is 1

//
// Sixth stage divider (6)
//
SRL16E srl6 (
    .Q   (stage6),
    .A0  (1'b1),
    .A1  (1'b0),
    .A2  (1'b1),
    .A3  (1'b0),
    .CE  (ce_1to4 & stage5),
    .CLK (clk),
    .D   (stage6));

// synthesis translate_off
defparam srl6.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl6 is 1


// 
// The fast, mid, and slow FFs represent the final stages of the divider chain.
//
assign ce_fast = ce_1to4 & stage5 & stage6;

always @ (posedge clk)
    if (ce_fast)
        fast <= ~fast;

always @ (posedge clk)
    if (ce_fast & fast)
        mid <= ~mid;

always @ (posedge clk)
    if (ce_fast & fast & mid)
        slow <= ~slow;

endmodule