hdsdi_rx_crc.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: hdsdi_rx_crc.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-08-23 13:06:27-06 $
// /___/   /\    Date Created: May 21, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: hdsdi_rx_crc.v,rcs $
// Revision 1.1  2004-08-23 13:06:27-06  jsnow
// Comment changes only.
//
// Revision 1.0  2004-05-21 13:47:25-06  jsnow
// Initial Revision
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

This module calculates the CRC value for a line and compares it to the received
CRC value. The module does this for both the Y and C channels. If a CRC error
is detected, the corresponding CRC error output is asserted high. This output
remains asserted for one video line time, until the next CRC check is made.

The module also captures the line number values for the two channels and 
outputs them. The line number values are valid for the entire line time. 

--------------------------------------------------------------------------------
*/

//`timescale 1ns / 1ns

module hdsdi_rx_crc (
    clk,                            // receiver clock
    rst,                            // reset signal
    ce,                             // clock enable input
    c_video,                        // C channel video input port
    y_video,                        // Y channel video input port
    trs,                            // TRS signal asserted during all 4 words of TRS
    c_crc_err,                      // C channel CRC error detected
    y_crc_err,                      // Y channel CRC error detected
    c_line_num,                     // C channel received line number
    y_line_num                      // Y channel received line number
);

// IO definitions   
input               clk;
input               ce;
input               rst;
input   [9:0]       c_video;
input   [9:0]       y_video;
input               trs;
output              c_crc_err;
output              y_crc_err;
output  [10:0]      c_line_num;
output  [10:0]      y_line_num;

reg                 c_crc_err;
reg                 y_crc_err;
reg     [10:0]      c_line_num;
reg     [10:0]      y_line_num;

// Internal wires
reg     [17:0]      c_rx_crc;
reg     [17:0]      y_rx_crc;
wire    [17:0]      c_calc_crc;
wire    [17:0]      y_calc_crc;
reg     [7:0]       trslncrc;
reg                 crc_clr;
reg                 crc_en;
reg     [6:0]       c_line_num_int;
reg     [6:0]       y_line_num_int;

//
// CRC generator modules
//
hdsdi_crc crc_C (
    .clk            (clk),
    .ce             (ce & crc_en),
    .rst            (rst),
    .clr            (crc_clr),
    .d              (c_video),
    .crc_out        (c_calc_crc)
);

hdsdi_crc crc_Y (
    .clk            (clk),
    .ce             (ce & crc_en),
    .rst            (rst),
    .clr            (crc_clr),
    .d              (y_video),
    .crc_out        (y_calc_crc)
);


//
// trslncrc generator
//
// This code generates timing signals indicating where the CRC and LN words
// are located in the EAV symbol.
//
always @ (posedge clk or posedge rst)
    if (rst)
        trslncrc <= 0;
    else if (ce)
        begin
            if (trs & ~trslncrc[0] & ~trslncrc[1] & ~trslncrc[2])
                trslncrc[0] <= 1'b1;
            else
                trslncrc[0] <= 1'b0;
            trslncrc[7:1] <= {trslncrc[6:3], trslncrc[2] & y_video[6], trslncrc[1:0]};
        end

//
// crc_clr signal
//
// The crc_clr signal controls when the CRC generator's accumulation register
// gets reset to begin calculating the CRC for a new line.
//
always @ (posedge clk or posedge rst)
    if (rst)
        crc_clr <= 1'b0;
    else if (ce)
        begin
            if (trslncrc[2] & ~y_video[6])
                crc_clr <= 1'b1;
            else
                crc_clr <= 1'b0;
        end
        
//
// crc_en signal
//
// The crc_en signal controls which words are included in the CRC calculation.
//
always @ (posedge clk or posedge rst)
    if (rst)
        crc_en <= 1'b0;
    else if (ce)
        begin
            if (trslncrc[2] & ~y_video[6])
                crc_en <= 1'b1;
            else if (trslncrc[4])
                crc_en <= 1'b0;
        end
        
//
// received CRC registers
//
// These registers hold the received CRC words from the input video stream.
//
always @ (posedge clk or posedge rst)
    if (rst)
        begin
            c_rx_crc <= 0;
            y_rx_crc <= 0;
        end
    else if (ce)
        begin
            if (trslncrc[5])
                begin
                    c_rx_crc[8:0] <= c_video[8:0];
                    y_rx_crc[8:0] <= y_video[8:0];
                end
            else if (trslncrc[6])
                begin
                    c_rx_crc[17:9] <= c_video[8:0];
                    y_rx_crc[17:9] <= y_video[8:0];
                end
        end

//
// CRC comparators
//
// Compare the received CRC values against the calculated CRCs.
//
always @ (posedge clk or posedge rst)
    if (rst)
        begin
            c_crc_err <= 1'b0;
            y_crc_err <= 1'b0;
        end
    else if (ce & trslncrc[7])
        begin
            if (c_rx_crc == c_calc_crc)
                c_crc_err <= 1'b0;
            else
                c_crc_err <= 1'b1;

            if (y_rx_crc == y_calc_crc)
                y_crc_err <= 1'b0;
            else
                y_crc_err <= 1'b1;
        end

//
// line number registers
//
// These registers hold the line number values from the input video stream.
//
always @ (posedge clk or posedge rst)
    if (rst)
        begin
            c_line_num_int <= 0;
            y_line_num_int <= 0;
            c_line_num <= 0;
            y_line_num <= 0;
        end
    else if (ce)
        begin
            if (trslncrc[3])
                begin
                    c_line_num_int <= c_video[8:2];
                    y_line_num_int <= y_video[8:2];
                end
            else if (trslncrc[4])
                begin
                    c_line_num <= {c_video[5:2], c_line_num_int};
                    y_line_num <= {y_video[5:2], y_line_num_int};
                end
        end

endmodule