pd_hd_vcxo.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: pd_HD_VCXO.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-12-09 13:59:09-07 $
// /___/   /\    Date Created: May 28, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: pd_HD_VCXO.v,rcs $
// Revision 1.1  2004-12-09 13:59:09-07  jsnow
// Cosmetic changes only.
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

This module is the low level of the phase detector used in conjuction with an
external VCXO and loop filter to implement a PLL for jitter reducing the
recovered clock from the Rocket IO transceiver in a HD-SDI pass-through
application.

*/
module  pd_HD_VCXO (
    //inputs
    vco,
    refclk,
    reset,
    vcoisfast,
    vcoisslow,
    vco_tc,
    refclk_tc
    );

//----------------------------------------------------------------------------
// Signal declarations
//

// port declarations
input   vco;
input   refclk;
input   reset;

output  vcoisfast;
output  vcoisslow;
output  vco_tc ;
output  refclk_tc;

// local signals
wire    vcoisfast;
wire    vcoisslow;
wire    pd_rst;



//-----------------------------------------------------------------------------
// divide counter,  
// divide vcxo (74.25MHz) by 74 to get ~1MHz the comparison 
// frequency.
// 128 - 55(0x37; 7'b011_0111) + 1 = 74 .
//
reg [7:2]   vcocount;   //8bits - 2bits = 5bits
reg [3:0]   vcocntlow;
wire        vco_tc       /* synthesis syn_keep = 1 */ ;
wire        vcocntlow_tc /* synthesis syn_keep = 1 */ ;

assign vco_tc = vcocount[7] | reset ;
assign vcocntlow_tc = vcocntlow[3] ;

always @ (posedge vco ) begin 
    if (vco_tc) begin
        vcocount    <= #1 6'b0011_01 ;
    end
    else if( vcocntlow_tc ) begin
        vcocount    <= #1 vcocount + 1;
    end
end

//-----------------------------------------------------------------------------
// lower 2 bits of the vco counter.
// shift reg counter is one hot code;
// bit 0 is 2'b00
// bit 1 is 2'b01
// bit 2 is 2'b10
// bit 3 is 2'b11
//
always @ (posedge vco ) begin 
    if (vco_tc) begin
        vcocntlow   <= #1 4'b1000;  // init to 3
    end
    else begin
        vcocntlow   <= #1 {vcocntlow[2:0], vcocntlow[3]};
    end
end

//-----------------------------------------------------------------------------
reg [7:2]   refclkcount;
reg [3:0]   refclkcntlow ;
wire        refclk_tc /* synthesis syn_keep = 1 */ ;
wire        refclkcntlow_tc /* synthesis syn_keep = 1 */ ;

assign refclk_tc = refclkcount[7] | reset;
assign refclkcntlow_tc = refclkcntlow[3];

//-----------------------------------------------------------------------------
// ref clock divider
// divide the ref clock (74.25MHz) by 74 to get compare freq of ~1MHz
// 128 - 55(0x37; 7'b011_0111) + 1 = 74 
//
always @ (posedge refclk ) begin 
    if (refclk_tc) begin 
        refclkcount     <= #1 6'b0011_01;
    end
    else if ( refclkcntlow_tc ) begin
        refclkcount <= #1 refclkcount + 1;
    end
end

//-----------------------------------------------------------------------------
// lower 2 bits of the ref counter.
// shift reg counter is one hot code;
// bit 0 is 2'b00
// bit 1 is 2'b01
// bit 2 is 2'b10
// bit 3 is 2'b11
//
always @ (posedge refclk ) begin 
    if (refclk_tc) begin
        refclkcntlow    <= #1 4'b1000;  //the "01" part of the 0x21
    end
    else begin
        refclkcntlow    <= #1 {refclkcntlow[2:0], refclkcntlow[3]};
    end
end

//----------------------------------------------------------------------------
//phase detect for reference
//
// set on the rising edge of the vco /ref
// pdetfast is active when the vco is faster than the ref xtal
// pdetslow is active when the vco is slower than the ref xtal
//
FDC pdfastreg     ( .D(1'b1), .C(vco_tc),    .CLR(pd_rst), .Q(vcoisfast));
FDC pdslowreg     ( .D(1'b1), .C(refclk_tc), .CLR(pd_rst), .Q(vcoisslow));
LUT2 pdrst_and2_0 (.I0(vcoisfast), .I1(vcoisslow), .O(pd_rst));

// synthesis attribute init of pdrst_and2_0 is 8 ;
// synthesis translate_off
defparam pdrst_and2_0.INIT = 4'h8;  //pdetfast & pdetslow
// synthesis translate_on

endmodule