multigenhd_vert.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2005 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: multigenHD_vert.v,rcs $
//  /   /        Date Last Modified:  $Date: 2005-01-05 10:25:00-07 $
// /___/   /\    Date Created: Jan 5, 2005 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: multigenHD_vert.v,rcs $
// Revision 1.1  2005-01-05 10:25:00-07  jsnow
// Header update.
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
This file contains the vertical sequencer for the HD video pattern generator.
A block RAM is used as a finite state machine, sequencing through the various
vertical sections of each video pattern. The module outputs a v_band code 
indicating which vertical portion of the video pattern should be displayed.      
*/

module multigenHD_vert (
    input   wire        clk,            // word-rate clock
    input   wire        rst,            // async reset
    input   wire        ce,             // clock enable
    input   wire [2:0]  std,            // selects video format
    input   wire [1:0]  pattern,        // 00 = RP 219 colorbars, X1 = RP 198 checkfield, 10 = 75% colorbars
    input   wire        h_counter_lsb,  // LSB of the horz section's h_counter
    input   wire        v_inc,          // causes the vertical counter to increment
    output  wire [2:0]  v_band,         // vertical band code output
    output  wire        v,              // vertical blanking interval indicator
    output  wire        f,              // odd/even field bit
    output  wire        first_line,     // asserted during first active line
    output  wire        y_ramp_inc_sel, // controls output sections Y-Ramp increment MUX
    output  wire [10:0] line_num        // current vertical line number
);

//-----------------------------------------------------------------------------
// Parameter definitions
//

//
// This group of parameters defines the bit widths of various fields in the
// module. 
//
parameter VID_WIDTH     = 10;                   // Width of video components
parameter VCNT_WIDTH    = 11;                   // Width of v_counter
parameter VRGN_WIDTH    = 5;                    // Width of v_region counter
parameter VBAND_WIDTH   = 3;                    // Width of vband code

parameter V_EVNT_WIDTH  = VCNT_WIDTH;           // Width of v_next_evnt
 
parameter VID_MSB       = VID_WIDTH - 1;        // MS bit # of video data path
parameter VCNT_MSB      = VCNT_WIDTH - 1;       // MS bit # of v_counter
parameter VRGN_MSB      = VRGN_WIDTH - 1;       // MS bit # of v_region counter
parameter VBAND_MSB     = VBAND_WIDTH - 1;      // MS bit # of vband code
parameter V_EVNT_MSB    = V_EVNT_WIDTH - 1;     // MS bit # of v_next_evnt

//
// The group of parameters defines the vertical regions from the vertical ROM.
// Note that the vertical ROM generates a 5-bit vertical region code and a 3-bit
// vertical band code. The region code is essentially the current state of the
// vertical state machine and feeds back to the input of the vertical ROM.
// The vertical band code is sent to the color ROM to indicate the current
// vertical pattern band.
//
parameter [VRGN_MSB:0]
    VRGN_FM0_F0_VB_0    = 0,    // frame 0, field 0, first vertical blanking interval
    VRGN_FM0_F0_1ST_ACT = 1,    // frame 0, field 0, first active line (for CEQ polarity)
    VRGN_FM0_F0_PAT1    = 2,    // frame 0, field 0, pattern 1 or cable eq pattern
    VRGN_FM0_F0_PAT2    = 3,    // frame 0, field 0, pattern 2 or PLL pattern
    VRGN_FM0_F0_PAT3    = 4,    // frame 0, field 0, pattern 3
    VRGN_FM0_F0_PAT4    = 5,    // frame 0, field 0, pattern 4
    VRGN_FM0_F0_VB_1    = 6,    // frame 0, field 0, second vertical blanking interval
    VRGN_FM0_F1_VB_0    = 7,    // frame 0, field 1, first vertical blanking interval
    VRGN_FM0_F1_PAT1    = 8,    // frame 0, field 1, pattern 1 or cable eq pattern
    VRGN_FM0_F1_PAT2    = 9,    // frame 0, field 1, pattern 2 or PLL pattern
    VRGN_FM0_F1_PAT3    = 10,   // frame 0, field 1, pattern 3
    VRGN_FM0_F1_PAT4    = 11,   // frame 0, field 1, pattern 4
    VRGN_FM0_F1_VB_1    = 12,   // frame 0, field 1, second vertical blanking interval
    VRGN_FM0_CLRV       = 13,   // frame 0 clears the vertical counter back to 1
    VRGN_X14            = 14,   // unused
    VRGN_X15            = 15,   // unused
    VRGN_FM1_F0_VB_0    = 16,   // frame 1, field 0, first vertical blanking interval
    VRGN_FM1_F0_PAT1    = 17,   // frame 1, field 0, pattern 1 or cable eq pattern
    VRGN_FM1_F0_PAT2    = 18,   // frame 1, field 0, pattern 2 or PLL pattern
    VRGN_FM1_F0_PAT3    = 19,   // frame 1, field 0, pattern 3
    VRGN_FM1_F0_PAT4    = 20,   // frame 1, field 0, pattern 4
    VRGN_FM1_F0_VB_1    = 21,   // frame 1, field 0, second vertical blanking interval
    VRGN_X22            = 22,   // unused
    VRGN_FM1_F1_VB_0    = 23,   // frame 1, field 1, first vertical blanking interval
    VRGN_FM1_F1_PAT1    = 24,   // frame 1, field 1, pattern 1 or cable eq pattern
    VRGN_FM1_F1_PAT2    = 25,   // frame 1, field 1, pattern 2 or PLL pattern
    VRGN_FM1_F1_PAT3    = 26,   // frame 1, field 1, pattern 3
    VRGN_FM1_F1_PAT4    = 27,   // frame 1, field 1, pattern 4
    VRGN_FM1_F1_VB_1    = 28,   // frame 1, field 1, second vertical blanking interval
    VRGN_FM1_CLRV       = 29,   // frame 1 clears the vertical counter back to 1
    VRGN_X30            = 30,   // unused
    VRGN_RST            = 31;   // initial state after reset

parameter [VBAND_MSB:0]
    VBAND_VB            = 0,    // vertical blanking interval
    VBAND_PAT1          = 1,    // pattern 1
    VBAND_PAT2          = 2,    // pattern 2
    VBAND_PAT3          = 3,    // pattern 3
    VBAND_PAT4          = 4,    // pattern 4
    VBAND_CEQ           = 5,    // cable equalization pattern
    VBAND_PLL           = 6,    // PLL pattern
    VBAND_X7            = 7;    // unused

//-----------------------------------------------------------------------------
// Signal definitions
//

wire    [31:0]          vrom_out;       // VROM output
reg     [VCNT_MSB:0]    v_counter;      // vertical counter
wire    [V_EVNT_MSB:0]  v_next_evnt;    // next vertical event
wire                    v_evnt_match;   // output of vertical event comparator
wire                    vrom_en;        // EN input to vertical ROM
wire    [VRGN_MSB:0]    v_region;       // current vertical region
wire    [VBAND_MSB:0]   v_band_rom;     // VBAND for most patterns
wire    [VBAND_MSB:0]   v_band_75_rom;  // VBAND for 75% color bars pattern
wire                    v_clr;          // vertical counter clear signal
wire    [31:0]          GND32 = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
wire    [3:0]           GND4 =  4'b0000;

//
// Vertical ROM
//

// Simulation initialization code VROM
// Created by multigenHD_romgen.v
// Video format mapping:
//   000 =  SMPTE 295M - 1080i  25Hz (1250 lines/frame)
//   001 =  SMPTE 274M - 1080sF 24Hz & 23.98Hz         
//   002 =  SMPTE 274M - 1080i  30Hz & 29.97 Hz        
//   003 =  SMPTE 274M - 1080i  25Hz                   
//   004 =  SMPTE 274M - 1080p  30Hz & 29.97Hz         
//   005 =  SMPTE 274M - 1080p  25Hz                   
//   006 =  SMPTE 274M - 1080p  24Hz & 23.98Hz         
//   007 =  SMPTE 296M - 720p   60Hz & 59.94Hz         
//synthesis translate_off
defparam
VROM.INIT = 36'h00048FFFF,
VROM.SRVAL = 36'h00048FFFF,
VROM.WRITE_MODE = "READ_FIRST",
VROM.INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
VROM.INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
VROM.INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
VROM.INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
VROM.INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
VROM.INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
VROM.INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
VROM.INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
VROM.INIT_00 = 256'h0018582800084E2702044D8602033CA5020237040201316302810A2200080A01,
VROM.INIT_01 = 256'h00089C4000089C4000589C5000189C2D02149BAC02138ACB0212852A02117F89,
VROM.INIT_02 = 256'h0038583800089C4000284E3702244D9502233CB4022237130221317200280A11,
VROM.INIT_03 = 256'h0008002000089C4000789C4000389C3D02349BBC02338ADB0232853A02317F99,
VROM.INIT_04 = 256'h0018582800084E2702040006020300050C064D860A052BC30A850A2200080A01,
VROM.INIT_05 = 256'h00089C4000089C4000589C5000189C2D0214000C0213000B0C169BAC0A1579E9,
VROM.INIT_06 = 256'h0038583800089C4000284E3702240015022300140C264D950A252BD200280A11,
VROM.INIT_07 = 256'h0008002000089C4000789C4000389C3D0234001C0233001B0C369BBC0A3579F9,
VROM.INIT_08 = 256'h001848E800084667020446060203352502022F84020129E3028102A200080281,
VROM.INIT_09 = 256'h00088CA000088CA000588CB000188C8D02148C6C02137B8B021275EA02117049,
VROM.INIT_0A = 256'h003848F800088CA000284677022446150223353402222F93022129F200280291,
VROM.INIT_0B = 256'h0008002000088CA000788CA000388C9D02348C7C02337B9B023275FA02317059,
VROM.INIT_0C = 256'h001848E80008466702040006020300050C0646060A0524430A8502A200080281,
VROM.INIT_0D = 256'h00088CA000088CA000588CB000188C8D0214000C0213000B0C168C6C0A156AA9,
VROM.INIT_0E = 256'h003848F800088CA00028467702240015022300140C2646150A25245200280291,
VROM.INIT_0F = 256'h0008002000088CA000788CA000388C9D0234001C0233001B0C368C7C0A356AB9,
VROM.INIT_10 = 256'h001848E800084667020446060203352502022F84020129E3028102A200080281,
VROM.INIT_11 = 256'h00088CA000088CA000588CB000188C8D02148C6C02137B8B021275EA02117049,
VROM.INIT_12 = 256'h003848F800088CA000284677022446150223353402222F93022129F200280291,
VROM.INIT_13 = 256'h0008002000088CA000788CA000388C9D02348C7C02337B9B023275FA02317059,
VROM.INIT_14 = 256'h001848E80008466702040006020300050C0646060A0524430A8502A200080281,
VROM.INIT_15 = 256'h00088CA000088CA000588CB000188C8D0214000C0213000B0C168C6C0A156AA9,
VROM.INIT_16 = 256'h003848F800088CA00028467702240015022300140C2646150A25245200280291,