hd_pass_ics664.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//
IBUF_LVCMOS25 XO33 (
    .O      (clk_33M),
    .I      (clk_33M_in));

BUFG BUFG33M (
    .O      (gclk_33M),
    .I      (clk_33M));

OBUF_LVCMOS25 ACECLKEN (
    .O      (ace_clk_en),
    .I      (1'b0));

//
// LED control block
//
led_control LEDC (
    .clk            (gclk_33M),
    .mr_tx2_on      (1'b1),
    .mr_tx2_fast    (1'b0),
    .mr_tx2_slow    (1'b0),
    .mr_tx1_on      (1'b1),     
    .mr_tx1_fast    (1'b0),
    .mr_tx1_slow    (1'b0),
    .mr_rx_on       (rx_heartbeat),
    .mr_rx_fast     (1'b0),
    .mr_rx_slow     (1'b0),
    .asi_tx_on      (1'b0),
    .asi_tx_fast    (1'b0),
    .asi_tx_slow    (1'b0),
    .sdi_rx_on      (1'b0),
    .sdi_rx_fast    (1'b0),
    .sdi_rx_slow    (1'b0),
    .sdi_tx_on      (1'b0),
    .sdi_tx_fast    (1'b0),
    .sdi_tx_slow    (1'b0),
    .mr_sync_on     (rx_locked),
    .mr_sync_fast   (1'b0),
    .mr_sync_slow   (~rx_locked),
    .mr_hd_on       (rate_sel),
    .mr_hd_fast     (1'b0),
    .mr_hd_slow     (1'b0),
    .mr_rate_on     (rx_format[3]),
    .mr_rate_fast   (1'b0),
    .mr_rate_slow   (1'b0),
    .sdi_sync_on    (rx_format[2]),
    .sdi_sync_fast  (1'b0),
    .sdi_sync_slow  (1'b0),                
    .sdi_rate_on    (rx_format[1]),
    .sdi_rate_fast  (1'b0),
    .sdi_rate_slow  (1'b0),
    .mode_mr_on     (rx_format[0]),
    .mode_mr_fast   (1'b0),
    .mode_mr_slow   (1'b0),
    .mode_sdi_on    (1'b0),
    .mode_sdi_fast  (1'b0),
    .mode_sdi_slow  (1'b0),
    .mode_asi_on    (1'b0),
    .mode_asi_fast  (crc_err_ff),
    .mode_asi_slow  (1'b0),

    .mr_tx2_led     (mr_tx2_led_out),
    .mr_tx1_led     (mr_tx1_led_out),
    .mr_rx_led      (mr_rx_led_out),
    .asi_tx_led     (asi_tx_led_out),
    .sdi_rx_led     (sdi_rx_led_out),
    .sdi_tx_led     (sdi_tx_led_out),
    .mr_sync_led    (mr_sync_led_out),
    .mr_hd_led      (mr_hd_led_out),
    .mr_rate_led    (mr_rate_led_out),
    .sdi_sync_led   (sdi_sync_led_out),
    .sdi_rate_led   (sdi_rate_led_out),
    .mode_mr_led    (mode_mr_led_out),
    .mode_sdi_led   (mode_sdi_led_out),
    .mode_asi_led   (mode_asi_led_out)
);

//-----------------------------------------------------------------------------
// HD-SDI Pass-through Section
//
                      
//
// RocketIO Transceiver
//
// This is the RocketIO transceiver. Inside this module are bit-swappers 
// needed to match the bit order of HD-SDI (LSB first) to the bit order of
// the Rocket IO module (MSB first). 
//
hdsdi_rio_refclk RIO1 (
    .brefclk        (1'b0),
    .brefclk2       (1'b0),
    .refclk         (clk_ics664),
    .refclk2        (1'b0),
    .refclk_sel     (1'b0),
    .rst            (1'b0),
    .loopback_en    (1'b0),
    .loopback_mode  (1'b0),
    .txinhibit      (1'b0),
    .txdata         (tx_data),
    .txusrclk       (rx_usrclk),
    .txusrclk2      (rx_usrclk),
    .rxusrclk       (rx_usrclk),
    .rxusrclk2      (rx_usrclk),
    .dcm_locked     (1'b1),
    .rxp            (mr_rx_rxp),
    .rxn            (mr_rx_rxn),
    .rxdata         (rx_data),
    .rxrecclk       (rx_recclk),
    .txp            (mr_tx1_txp),
    .txn            (mr_tx1_txn));

BUFG RXCLK_BUFG (.O(rx_usrclk), .I(rx_recclk));

//
// Phase detector for HD VCXO PLL
//
// This PLL locks the HD VCXO to the clock recovered by the RocketIO receiver
// and produces a low jitter clock running at the same frequency as the 
// recovered clock.
//
phasedetHD phasedet (
    .vco(clk_ics664),
    .refclk(rx_recclk),      
    .reset(1'b0),
    .mkvcofaster(make_vcxo_faster),
    .mkvcoslower(make_vcxo_slower),
    .vco_tc(),
    .refclk_tc()
);

//
// HD-SDI receiver
//
// This module decscrambles and frames the data received by the RocketIO
// receiver. The recovered data is checked for errors.
//

hdsdi_rx2 RX (
    .clk            (rx_usrclk),
    .ce             (1'b1),
    .rst            (1'b0),
    .dec_bypass     (1'b0),
    .frame_en       (rx_nsp),
    .rxdata         (rx_data),
    .c_out          (rx_vid_c),
    .y_out          (rx_vid_y),
    .nsp            (rx_nsp),
    .trs            (),
    .xyz            (rx_xyz),
    .eav            (rx_eav),
    .sav            (rx_sav),
    .trs_err        (rx_trs_err),
    .rx_ln          (rx_ln),
    .gen_ln         (rx_new_ln),
    .gen_ln_valid   (rx_new_ln_valid),
    .c_crc_err      (rx_c_crc_err),
    .y_crc_err      (rx_y_crc_err),
    .std            (rx_format),
    .std_locked     (rx_locked));

//
// Bit rate detection & control module
//
hdsdi_rx_autorate ARATE (
    .clk            (rx_usrclk),
    .rst            (1'b0),
    .sav            (rx_sav),
    .trs_err        (rx_trs_err),
    .y_crc_err      (rx_y_crc_err),
    .c_crc_err      (rx_c_crc_err),
    .refclksel      (rate_sel)
);

//
// This optional module generates some decoding video timing information.
//
hdsdi_rx_timing TMG (
    .clk            (rx_usrclk),
    .rst            (1'b0),
    .ln_in          (rx_ln),
    .vid_in         (rx_vid_y),
    .xyz            (rx_xyz),
    .sav            (rx_sav),
    .frame_start    (),
    .field          (rx_field),
    .v_blank        (rx_v_blank),
    .h_blank        (rx_h_blank),
    .horz_position  ());

//
// This module divides the TRS signal frequency down to a visible flash rate
// to drive the Rx Heartbeat LED.
//
rx_heartbeat HBEAT (
    .clk            (rx_usrclk),
    .xyz            (rx_xyz),
    .trs_err        (rx_trs_err),
    .heartbeat      (rx_heartbeat));

//
// Error capture flip-flop
//
// This flip-flop get set when CRC errors are detected and is reset with
// push button 3.
//

always @ (posedge rx_usrclk)
    if (clr_errs)
        crc_err_ff <= 1'b0;
    else if (rx_locked)
        if (rx_c_crc_err | rx_y_crc_err)
            crc_err_ff <= 1'b1;

//
// hdsdi_tx_path
//
// This module contains the line number insertion logic, CRC generation and
// insertion logic, and the HD-SDI encoder.
//
hdsdi_tx_path TXPATH1 (
    .clk            (rx_usrclk),
    .rst            (1'b0),
    .ce             (1'b1),
    .c_in           (rx_vid_c),
    .y_in           (rx_vid_y),
    .nrzi           (1'b1),             // always enable the NRZI-to-NRZ conversion
    .scram          (1'b1),             // always enable the scrambler
    .insert_crc     (insert_new_crc),   // DIP switch controls CRC insertion/pass through
    .force_crc_err  (1'b0),
    .insert_ln      (rx_new_ln_valid & insert_new_ln),  // DIP switch controls LN insertion/pass through
    .ln             (rx_new_ln),
    .eav            (rx_eav),
    .sav            (rx_sav),
    .q              (tx_data));

//-----------------------------------------------------------------------------
// Stand-alone transmitter section
//
// This transmitter drives the MR-Tx2 output connector with HD-SDI video
// generated by an internal video pattern generator.
//

//
// Input registers for the video standard select inputs (dipsw[7:5])
//
// The video format generated by the multigenHD video pattern generator is
// determined by three DIP switches. The registers below synchronize these
// inputs to the txusrclk.
//
always @ (posedge tx2_usrclk)
    stdsel_reg <= dipsw[7:5];

always @ (posedge tx2_usrclk)
    stdsel_syncreg <= stdsel_reg;

//
// Video generator
//
// This pattern generator can produce eight different video formats that are
// HD-SDI compatible.
//
assign tx2_patsel[0] = dipsw[2] & dipsw[1];
assign tx2_patsel[1] = dipsw[2];
assign tx2_insert_logo = ~dipsw[2] & ~dipsw[1];

multigenHD_logo VIDGEN (
    .clk            (tx2_usrclk),
    .rst            (1'b0),
    .ce             (1'b1),
    .std            (stdsel_syncreg),
    .pattern        (tx2_patsel),
    .user_opt       (2'b00),
    .insert_logo    (tx2_insert_logo),
    .y              (tx2_vid_y),
    .c              (tx2_vid_c),
    .h_blank        (),
    .v_blank        (),
    .field          (),
    .trs            (),
    .xyz            (tx2_xyz),
    .line_num       (tx2_ln));
    
assign tx2_sav = ~tx2_vid_y[6] & tx2_xyz;
assign tx2_eav =  tx2_vid_y[6] & tx2_xyz;

//
// HD-SDI transmitter
//
// This module does line number generation and insertion, CRC generation and
// insertion, and HD-SDI encoding.
//
hdsdi_tx_path TXPATH2 (
    .clk            (tx2_usrclk),
    .rst            (1'b0),
    .ce             (1'b1),
    .c_in           (tx2_vid_c),
    .y_in           (tx2_vid_y),
    .nrzi           (1'b1),         // always enable the NRZI-to-NRZ conversion
    .scram          (1'b1),         // always enable the scrambler
    .insert_crc     (1'b1),         // always enable insertion of the CRCs
    .force_crc_err  (tx2_force_crc_err),
    .insert_ln      (1'b1),         // always enable insertion of line numbers
    .ln             (tx2_ln),
    .eav            (tx2_eav),
    .sav            (tx2_sav),
    .q              (tx2_data));

                      
//
// RocketIO Transceiver
//
// This is the RocketIO transceiver. Inside this module are bit-swappers 
// needed to match the bit order of HD-SDI (LSB first) to the bit order of
// the RocketIO module (MSB first). 
//
hdsdi_rio RIO2 (
    .brefclk        (clk_74_17M),
    .brefclk2       (clk_74_25M),
    .refclk         (1'b0),
    .refclk2        (1'b0),
    .refclk_sel     (tx2_refclksel),
    .rst            (1'b0),
    .loopback_en    (1'b0),
    .loopback_mode  (1'b0),
    .txinhibit      (1'b0),
    .txdata         (tx2_data),
    .txusrclk       (tx2_usrclk),
    .txusrclk2      (tx2_usrclk),
    .rxusrclk       (tx2_usrclk),       // even though Rx is not used, rxusrclk should be running
    .rxusrclk2      (tx2_usrclk),
    .dcm_locked     (1'b1),
    .rxp            (mr_rx2_rxp),
    .rxn            (mr_rx2_rxn),
    .rxdata         (),
    .rxrecclk       (),
    .txp            (mr_tx2_txp),
    .txn            (mr_tx2_txn));

//-----------------------------------------------------------------------------
// Test signal outputs to board header
//
OBUF_LVCMOS25 TP0 (.I(rx_usrclk), .O(test_point[0]));
OBUF_LVCMOS25 TP1 (.I(rx_y_crc_err | rx_c_crc_err), .O(test_point[1]));
OBUF_LVCMOS25 TP2 (.I(rx_field), .O(test_point[2]));
OBUF_LVCMOS25 TP3 (.I(rx_v_blank), .O(test_point[3]));
OBUF_LVCMOS25 TP4 (.I(rx_h_blank), .O(test_point[4]));
OBUF_LVCMOS25 TP5 (.I(1'b0), .O(test_point[5]));
OBUF_LVCMOS25 TP6 (.I(1'b0), .O(test_point[6]));
OBUF_LVCMOS25 TP7 (.I(1'b0), .O(test_point[7]));
OBUF_LVCMOS25 TP8 (.I(1'b0), .O(test_point[8]));
OBUF_LVCMOS25 TP9 (.I(1'b0), .O(test_point[9]));


//-----------------------------------------------------------------------------
// Output buffers required to drive SDV board components that are not used by
// this demo.
//

// HD-SDI VCXO

OBUF_LVCMOS33 HDVCXO_U (.I(1'b0), .O(hd_vcxo_up));
OBUF_LVCMOS33 HDVCXO_D (.I(1'b0), .O(hd_vcxo_down));

// SDI 270MHz VCO

OBUF_LVCMOS33 SDVCO_U (.I(1'b0), .O(sdi_vco_up));
OBUF_LVCMOS33 SDVCO_D (.I(1'b0), .O(sdi_vco_down));

// CY22394 PLL

OBUF_LVCMOS33 CYP_OE (.I(1'b0), .O(cypll_oe));
OBUF_LVCMOS33 CYP_S2 (.I(1'b0), .O(cypll_s2));
OBUF_LVCMOS33 CYP_SC (.I(1'b0), .O(cypll_sclk));
OBUF_LVCMOS33 CYP_SD (.I(1'b0), .O(cypll_sdat));

// ICS8745 PLL

OBUFDS_LVDS_25 I8745_COUT  (.I(1'b0), .O(ics8745_clkout_p), .OB(ics8745_clkout_n));
OBUF_LVCMOS25 I8745_SEL0   (.I(1'b0), .O(ics8745_sel[0]));
OBUF_LVCMOS25 I8745_SEL1   (.I(1'b0), .O(ics8745_sel[1]));
OBUF_LVCMOS25 I8745_SEL2   (.I(1'b0), .O(ics8745_sel[2]));
OBUF_LVCMOS25 I8745_SEL3   (.I(1'b0), .O(ics8745_sel[3]));
OBUF_LVCMOS25 I8745_PLLSEL (.I(1'b0), .O(ics8745_pll_sel));
OBUF_LVCMOS25 I8745_MR     (.I(1'b0), .O(ics8745_mr));

// SDI-Tx Port

OBUFDS_LVDS_25 SDI_TXD (.I(1'b0), .O(sdi_tx_dout_p), .OB(sdi_tx_dout_n));

// ASI-Tx Port
OBUFDS_LVDS_25 ASI_TXD (.I(1'b0), .O(asi_tx_p), .OB(asi_tx_n));

// RS-232 Port

OBUF_LVCMOS25 RS232TXD (.I(1'b0), .O(rs232_txd));
OBUF_LVCMOS25 RS232RTS (.I(1'b0), .O(rs232_rts));

endmodule