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📄 hd_sep_demo.ucf

📁 SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写
💻 UCF
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#------------------------------------------------------------------------------ 
# Copyright (c) 2004 Xilinx, Inc. 
# All Rights Reserved 
#------------------------------------------------------------------------------ 
#   ____  ____ 
#  /   /\/   / 
# /___/  \  /   Vendor: Xilinx 
# \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
#  \   \        Filename: $RCSfile: hd_sep_demo.ucf,rcs $
#  /   /        Date Last Modified:  $Date: 2005-06-24 08:57:10-06 $
# /___/   /\    Date Created: Dec 9, 2004 
# \   \  /  \ 
#  \___\/\___\ 
# 
#
# Revision History: 
# $Log: hd_sep_demo.ucf,rcs $
# Revision 1.2  2005-06-24 08:57:10-06  jsnow
# Modified location constraints for RocketIO to use / as hierachy sep.
#
# Revision 1.1  2004-12-09 12:59:37-07  jsnow
# XAPP577 version 1 release.
#
#------------------------------------------------------------------------------ 
#
#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
#     FOR A PARTICULAR PURPOSE.
#
#------------------------------------------------------------------------------ 
#
# User constraints file for the separate Rx & TX HD-SDI demo from XAPP577.
#
#------------------------------------------------------------------------------

#
# IOB location constraints
#
# Push buttons
#
NET "push_button1"  LOC = "AE1"  ;
NET "push_button2"  LOC = "AF2"  ;
NET "push_button3"  LOC = "AC3"  ;
#
# DIP switches
#
NET "dip_switches<0>"  LOC = "R4"  ;
NET "dip_switches<1>"  LOC = "R5"  ;
NET "dip_switches<2>"  LOC = "AB3"  ;
NET "dip_switches<3>"  LOC = "AB4"  ;
NET "dip_switches<4>"  LOC = "AC1"  ;
NET "dip_switches<5>"  LOC = "AC2"  ;
NET "dip_switches<6>"  LOC = "AD1"  ;
NET "dip_switches<7>"  LOC = "AD2"  ;
#
# GS1528 cable driver slew rate control outputs
#
NET "mr_tx1_slewrate"  LOC = "D1"  ;
NET "mr_tx2_slewrate"  LOC = "C1"  ;
#
# 74.2500MHz XO differential input pair
#
NET "clk_74_25M_n"  LOC = "B13" ;
NET "clk_74_25M_p"  LOC = "C13" ;
#
# 74.1758MHz XO differential input pair
#
NET "clk_74_17M_n"  LOC = "C14" ;
NET "clk_74_17M_p"  LOC = "B14" ;
#
# 33 MHz clock and clock enable output
#
NET "clk_33M_in"  LOC = "AC21"  ;
NET "ace_clk_en"  LOC = "AD21"  ;
#
# 270MHz VCO loop filter control outputs
#
NET "sdi_vco_down"  LOC = "M4"  ;
NET "sdi_vco_up"  LOC = "M3"  ;
#
# 27MHz VCXO loop filter control and control voltage select outputs
#
NET "vcxo_27M_down"  LOC = "M1"  ;
NET "vcxo_27M_down"  DRIVE = 2;
NET "vcxo_27M_down"  SLOW;
NET "vcxo_27M_sel"   LOC = "N7"  ;
NET "vcxo_27M_up"    LOC = "M2"  ;
NET "vcxo_27M_up"    DRIVE = 2;
NET "vcxo_27M_up"    SLOW;
#
# ICS660 PLL control outputs
#
NET "ics660_s<0>"  LOC = "A2"  ;
NET "ics660_s<1>"  LOC = "B1"  ;
NET "ics660_s<2>"  LOC = "C2"  ;
NET "ics660_s<3>"  LOC = "E4"  ;
NET "ics660_x1"  LOC = "AB15"  ;
#
# Cypress 22394 PLL control outputs
#
NET "cypll_oe"  LOC = "D2"  ;
NET "cypll_s2"  LOC = "N5"  ;
NET "cypll_sclk"  LOC = "N4"  ;
NET "cypll_sdat"  LOC = "N6"  ;
#
# ICS8745 PLL control outputs
#
NET "ics8745_clkout_n"  LOC = "AF19"  ;
NET "ics8745_clkout_p"  LOC = "AE19"  ;
NET "ics8745_mr"  LOC = "AA20"  ;
NET "ics8745_pll_sel"  LOC = "AC20"  ;
NET "ics8745_sel<0>"  LOC = "Y18"  ;
NET "ics8745_sel<1>"  LOC = "AB20"  ;
NET "ics8745_sel<2>"  LOC = "Y19"  ;
NET "ics8745_sel<3>"  LOC = "AA19"  ;
#
# SD-SDI Tx Output
#
NET "sdi_tx_dout_p"  LOC = "AC15"  ;
NET "sdi_tx_dout_n"  LOC = "AD15"  ;
#
# DVB-ASI Tx Output
#
NET "asi_tx_n"  LOC = "AC12"  ;
NET "asi_tx_p"  LOC = "AD12"  ;
#
# RS-232 Port Outputs
#
NET "rs232_rts"  LOC = "N22"  ;
NET "rs232_txd"  LOC = "N25"  ;
#
# LEDs
#
NET "asi_tx_led"  LOC = "M25"  ;
NET "mode_asi_led"  LOC = "R3"  ;
NET "mode_mr_led"  LOC = "P7"  ;
NET "mode_sdi_led"  LOC = "R2"  ;
NET "mr_hd_led"  LOC = "P3"  ;
NET "mr_rate_led"  LOC = "P4"  ;
NET "mr_rx_led"  LOC = "M26"  ;
NET "mr_sync_led"  LOC = "P2"  ;
NET "mr_tx1_led"  LOC = "N20"  ;
NET "mr_tx2_led"  LOC = "N21"  ;
NET "sdi_rate_led"  LOC = "P6"  ;
NET "sdi_rx_led"  LOC = "M24"  ;
NET "sdi_sync_led"  LOC = "P5"  ;
NET "sdi_tx_led"  LOC = "M23"  ;
#
# Test Points
#
NET "test_point<0>"  LOC = "A25" ;
NET "test_point<1>"  LOC = "B26" ;
NET "test_point<2>"  LOC = "C25" ;
NET "test_point<3>"  LOC = "C26" ;
NET "test_point<4>"  LOC = "D26" ;
NET "test_point<5>"  LOC = "E23" ;
NET "test_point<6>"  LOC = "E24" ;
NET "test_point<7>"  LOC = "E25" ;
NET "test_point<8>"  LOC = "E26" ;
NET "test_point<9>"  LOC = "G21" ;

#
# Rocket IO
#
INST "RIO1/RIO/GT" LOC = "GT_X1Y1"  ;
INST "RIO2/RIO/GT" LOC = "GT_X0Y1"  ;

#
#------------------------------------------------------------------------------
#
# Timing constraints
#
NET "clk_74_17M_n" TNM_NET = "clk_74_17M_n";
TIMESPEC "TS_clk_74_17M_n" = PERIOD "clk_74_17M_n" 75 MHz HIGH 50 % INPUT_JITTER 100 ps;
NET "clk_74_17M_p" TNM_NET = "clk_74_17M_p";
TIMESPEC "TS_clk_74_17M_p" = PERIOD "clk_74_17M_p" 75 MHz HIGH 50 % INPUT_JITTER 100 ps;
NET "clk_74_25M_n" TNM_NET = "clk_74_25M_n";
TIMESPEC "TS_clk_74_25M_n" = PERIOD "clk_74_25M_n" 75 MHz HIGH 50 % INPUT_JITTER 100 ps;
NET "clk_74_25M_p" TNM_NET = "clk_74_25M_p";
TIMESPEC "TS_clk_74_25M_p" = PERIOD "clk_74_25M_p" 75 MHz HIGH 50 % INPUT_JITTER 100 ps;
NET "clk_33M_in" TNM_NET = "clk_33M_in";
TIMESPEC "TS_clk_33M_in" = PERIOD "clk_33M_in" 35 MHz HIGH 50% INPUT_JITTER 100 ps;
NET "rx_recclk" TNM_NET = "rx_recclk";
TIMESPEC "TS_rx_recclk" = PERIOD "rx_recclk" 75 MHz HIGH 50 % INPUT_JITTER 100 ps;

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