hd_sep_demo.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: hd_sep_demo.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-12-09 13:00:03-07 $
// /___/   /\    Date Created: May 25, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: hd_sep_demo.v,rcs $
// Revision 1.2  2004-12-09 13:00:03-07  jsnow
// XAPP577 version 1 release.
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

This is the top level file for the SDV board HD-SDI separate Rx & Tx demo.

This demo has one HD-SDI transmitter driven from an internal video pattern
generator. It also has a separate HD-SDI receiver that will receive the
HD-SDI bitstream and check it for CRC errors. The Rx & Tx sections are totally
independent. Both interfaces support both HD-SDI bit rates. The receiver
automatically detects the bit rate of the incoming bitstream and adjusts to
receive it. The transmitter's bit rate is controlled by a DIP switch.

The DIP switches on the SDV board perform the following functions in this demo:

SW0: Determines the bit rate of the MR-Tx2 transmitter  
    OFF: 1.485 Gbps
    ON:  1.485/1.001 Gbps

SW[2:1]: Determine the video pattern transmitted by the MR-Tx2 transmitter
    OFF OFF: RP-198 HD-SDI checkfield (pathological patterns)
    OFF ON:  75% color bars
    ON  OFF: SMPTE RP-219 color bars without Xilinx logo
    ON  ON:  SMPTE RP-219 color bars with Xilinx logo inserted
     
SW3[4:2] Controls optional user selectable fields in the SMPTE RP-219 video
pattern

SW[7:5]: Determine the video format output by the MR-Tx2 transmitter
    OFF OFF OFF: SMPTE 296M - 720p   60 Hz or 59.94 Hz 
    OFF OFF ON:  SMPTE 274M - 1080p  24 Hz or 23.98 Hz
    OFF ON  OFF: SMPTE 274M - 1080p  25 Hz
    OFF ON  ON:  SMPTE 274M - 1080p  30 Hz & 29.97 Hz
    ON  OFF OFF: SMPTE 274M - 1080i  25 Hz
    ON  OFF ON:  SMPTE 274M - 1080i  30 Hz & 29.97 Hz
    ON  ON  OFF: SMPTE 274M - 1080sF 24 Hz & 23.98 Hz
    ON  ON  ON:  SMPTE 295M - 1080i  25 Hz (1250 lines/frame)

The pushbutton switches on the SDV board have the following functions:

SW2: FPGA global reset
SW3: Clear the receiver CRC error LED
SW4: Force a CRC error in the video transmitted by MR-Tx2

Received CRC errors are indicated by the flashing of the leftmost LED
immediately below the pushbuttons. Once a single CRC error is detected, this
LED will continue to flash until cleared by pushing pushbutton SW3.

The LED above the MR-Rx BNC connector will flash when video is being received.
This LED indicates the detection of valid TRS symbols in the video and is used
as a "heartbeat" indication -- showing that data is being received.

Some video related signals are output to the J13 testpoints:

Pin 1: The recovered clock from the MR-Rx receiver (before jitter reduction)
Pin 2: CRC error (not latched) -- pulses every time a CRC error is detected
Pin 3: Field indicator from received video
Pin 4: Vertical blanking indicator from received video
Pin 5: Horizontal blanking indicator from received video

--------------------------------------------------------------------------------
*/

module hd_sep_demo (
// Clock inputs    
    input   wire        clk_74_25M_p,       // 74.25MHz XO
    input   wire        clk_74_25M_n,
    input   wire        clk_74_17M_p,       // 74.1756MHz XO
    input   wire        clk_74_17M_n,
    input   wire        clk_33M_in,         // 33 MHz XO

// Clock control outputs
    output  wire        ace_clk_en,         // 33MHz clock enable

// Switch inputs
    input   wire        push_button1,  
    input   wire        push_button2,
    input   wire        push_button3,
    input   wire [7:0]  dip_switches,

// HD-SDI serial inputs, outputs, and slew rate control
    input   wire        mr_rx_rxp,          // Rocket IO receiver input
    input   wire        mr_rx_rxn,              
    output  wire        mr_tx1_txp,         // this RocketIO output pair is unused
    output  wire        mr_tx1_txn,
    output  wire        mr_tx1_slewrate,    // slew rate control for cable driver
    output  wire        mr_tx2_txp,         // Rocket IO transmitter output #2
    output  wire        mr_tx2_txn,         
    output  wire        mr_tx2_slewrate,    // slew rate control for cable driver
    input   wire        mr_rx2_rxp,         // this RocketIO input pair is unused
    input   wire        mr_rx2_rxn,

// LEDs
    output  wire        mr_tx2_led,             
    output  wire        mr_tx1_led,             
    output  wire        mr_rx_led,              
    output  wire        asi_tx_led,             
    output  wire        sdi_rx_led,             
    output  wire        sdi_tx_led,             
    output  wire        mr_sync_led,            
    output  wire        mr_hd_led,              
    output  wire        mr_rate_led,            
    output  wire        sdi_sync_led,           
    output  wire        sdi_rate_led,           
    output  wire        mode_mr_led,            
    output  wire        mode_sdi_led,           
    output  wire        mode_asi_led,   
    
// Test outputs
    output  wire [9:0]  test_point,            

// Outputs unused in this demo but required to be driven on the SDV Demo board
        
    output  wire        sdi_vco_up,
    output  wire        sdi_vco_down,
    output  wire        vcxo_27M_up,
    output  wire        vcxo_27M_down,
    output  wire        vcxo_27M_sel,
    output  wire [3:0]  ics660_s,
    output  wire        ics660_x1,
    output  wire        cypll_oe,
    output  wire        cypll_s2,
    output  wire        cypll_sclk,
    output  wire        cypll_sdat,
    output  wire        ics8745_clkout_p,
    output  wire        ics8745_clkout_n,
    output  wire [3:0]  ics8745_sel,
    output  wire        ics8745_pll_sel,
    output  wire        ics8745_mr,
    output  wire        sdi_tx_dout_p,
    output  wire        sdi_tx_dout_n,
    output  wire        asi_tx_p,
    output  wire        asi_tx_n,
    output  wire        rs232_txd,
    output  wire        rs232_rts
);

//-----------------------------------------------------------------------------
// Signal definitions
//

// Clock signals
wire            clk_74_25M;         // 74.25MHz clock after IOB
wire            clk_74_17M;         // 74.1758MHz clock after IOB
wire            clk_33M;            // 33MHz clock after IOB
wire            gclk_33M;           // global 33MHz clock

// Switch signals
wire [7:0]      dipsw;              // DIP switches after IOBs
wire            pb1;                // pushbutton 1 after IOB
wire            pb2;                // pushbutton 2 after IOB
wire            pb3;                // pushbutton 3 after IOB

// Internal LED control signals
wire            mr_tx2_led_out;
wire            mr_tx1_led_out;
wire            mr_rx_led_out;
wire            asi_tx_led_out;
wire            sdi_rx_led_out;
wire            sdi_tx_led_out;
wire            mr_sync_led_out;
wire            mr_hd_led_out;
wire            mr_rate_led_out;
wire            sdi_sync_led_out;
wire            sdi_rate_led_out;
wire            mode_mr_led_out;
wire            mode_sdi_led_out;
wire            mode_asi_led_out;   

// Signals for HD-SDI receiver
wire            rx_recclk;          // recovered clock from RocketIO receiver
wire            rx_usrclk;          // rx_recclk after BUFG
wire            rx_refclksel;       // selects Rx reference clock
wire [19:0]     rx_data;            // data from RocketIO receiver
wire            rx_nsp;             // new start position from framer
wire [9:0]      rx_vid_y;           // Y channel received video
wire [9:0]      rx_vid_c;           // C channel received video
wire [3:0]      rx_format;          // decoded video standard from hdsdi_autodetect_ln
wire            rx_locked;          // hdsdi_autodetect_ln is locked
wire            clr_errs;           // clear the error LED
reg             crc_err_ff;         // captures CRC errors
wire            rx_y_crc_err;       // Y channel CRC error from hdsdi_rx
wire            rx_c_crc_err;       // C channel CRC error from hdsdi_rx
wire            rx_trs_err;         // TRS error signal
wire            rx_xyz;             // xyz output of hdsdi_rx
wire            rx_sav;             // sav output of hdsdi_rx
wire            rx_eav;             // eav output of hdsdi_rx
wire            rx_field;           // field output from hdsdi_rx_timing
wire            rx_v_blank;         // v_blank output from hdsdi_rx_timing
wire            rx_h_blank;         // h_blank output from hdsdi_rx_timing
wire            rx_heartbeat;       // rx heartbeat signal for LED
wire [10:0]     rx_ln;              // rx line number

// Signals for HD-SDI transmitter
wire            tx_usrclk;          // global transmitter clock (BUFGMUX output)
wire            tx_refclksel;       // RocketIO reference clock select
reg  [2:0]      stdsel_reg;         // input register for the standard select inputs
reg  [2:0]      stdsel_syncreg;     // synchronization register for std select inputs
wire [9:0]      tx_vid_y;           // video pat gen Y channel output
wire [9:0]      tx_vid_c;           // video pat gen C channel output
wire [10:0]     tx_ln;              // video pat gen line number output
wire            tx_xyz;             // video pat gen XYZ word indicator
wire            tx_eav;             // EAV signal into transmitter 
wire            tx_sav;             // SAV signal into transmitter
wire [19:0]     tx_data;            // encoded data to RocketIO transmitter
wire            tx_force_crc_err;   // forces a CRC error on the Tx2 output
wire [1:0]      tx_patsel;          // pattern select for video pattern gen
wire            tx_insert_logo;     // Xilinx logo enable for pattern gen

//
// Instantiate the startup block so that push_button1 drives the global reset
//
STARTUP_VIRTEX2 STARTV2 (
    .CLK                (),
    .GSR                (~pb1),
    .GTS                ());


//-----------------------------------------------------------------------------
// I/O Buffers
//

//
// Push button switches
//
// PB1 is global reset
// PB2 resets the CRC error LED
// PB3 forces CRC transmission errors out MR-Tx2
//
IBUF_LVCMOS25 PB1 (.I(push_button1), .O(pb1));
IBUF_LVCMOS25 PB2 (.I(push_button2), .O(pb2));
IBUF_LVCMOS25 PB3 (.I(push_button3), .O(pb3));

assign clr_errs = ~pb2;
assign tx_force_crc_err = ~pb3;

//
// DIP switches
//
IBUF_LVCMOS25 SW0 (.I(dip_switches[0]), .O(dipsw[0]));
IBUF_LVCMOS25 SW1 (.I(dip_switches[1]), .O(dipsw[1]));
IBUF_LVCMOS25 SW2 (.I(dip_switches[2]), .O(dipsw[2]));
IBUF_LVCMOS25 SW3 (.I(dip_switches[3]), .O(dipsw[3]));
IBUF_LVCMOS25 SW4 (.I(dip_switches[4]), .O(dipsw[4]));
IBUF_LVCMOS25 SW5 (.I(dip_switches[5]), .O(dipsw[5]));
IBUF_LVCMOS25 SW6 (.I(dip_switches[6]), .O(dipsw[6]));
IBUF_LVCMOS25 SW7 (.I(dip_switches[7]), .O(dipsw[7]));

assign tx_refclksel = dipsw[0];

//
// LED Buffers
//
OBUF_LVCMOS25 LED0  (.I(mr_tx2_led_out),  .O(mr_tx2_led));
OBUF_LVCMOS25 LED1  (.I(mr_tx1_led_out),  .O(mr_tx1_led));
OBUF_LVCMOS25 LED2  (.I(mr_rx_led_out),   .O(mr_rx_led));
OBUF_LVCMOS25 LED3  (.I(asi_tx_led_out),  .O(asi_tx_led));
OBUF_LVCMOS25 LED4  (.I(sdi_rx_led_out),  .O(sdi_rx_led));
OBUF_LVCMOS25 LED5  (.I(sdi_tx_led_out),  .O(sdi_tx_led));
OBUF_LVCMOS25 LED6  (.I(mr_sync_led_out), .O(mr_sync_led));
OBUF_LVCMOS25 LED7  (.I(mr_hd_led_out),   .O(mr_hd_led));
OBUF_LVCMOS25 LED8  (.I(mr_rate_led_out), .O(mr_rate_led));
OBUF_LVCMOS25 LED9  (.I(sdi_sync_led_out),.O(sdi_sync_led));
OBUF_LVCMOS25 LED10 (.I(sdi_rate_led_out),.O(sdi_rate_led));
OBUF_LVCMOS25 LED11 (.I(mode_mr_led_out), .O(mode_mr_led));
OBUF_LVCMOS25 LED12 (.I(mode_sdi_led_out),.O(mode_sdi_led));
OBUF_LVCMOS25 LED13 (.I(mode_asi_led_out),.O(mode_asi_led));

//
// GS1528 Cable Driver slew rate control output
//
// The GS1528 cable driver has a slew rate control input that tells it whether
// to compliant with SDI or HD-SDI slew rates. In this demo, we are always
// transmitting HD-SDI, so we always force this signal low.
//
OBUF_LVCMOS33 MRTX2_SLEW (.I(1'b0), .O(mr_tx2_slewrate));
OBUF_LVCMOS33 MRTX1_SLEW (.I(1'b0), .O(mr_tx1_slewrate));

//
// 74.25M XO input buffer
//
IBUFGDS HDXO1 (
    .O      (clk_74_25M),
    .I      (clk_74_25M_p),
    .IB     (clk_74_25M_n));
// synthesis attribute CLOCK_SIGNAL of clk_74_25M_p is yes;
// synthesis attribute IOSTANDARD of HDXO1 is LVDSEXT_25_DT

//
// 74.1758MHz XO input buffer
//
IBUFGDS HDXOM (
    .O      (clk_74_17M),
    .I      (clk_74_17M_p),
    .IB     (clk_74_17M_n));
// synthesis attribute CLOCK_SIGNAL of clk_74_17M_p is yes;
// synthesis attribute IOSTANDARD of HDXOM is LVDSEXT_25_DT

//
// BUFGMUX to generate tx_usrclk
//
BUFGMUX BFG1 (
    .I0     (clk_74_17M),
    .I1     (clk_74_25M),
    .S      (tx_refclksel),
    .O      (tx_usrclk));

//
// 33MHz clock input buffer
//
// Note that the 33 MHz clock is only used for the LED control.
//
IBUF_LVCMOS25 XO33 (
    .O      (clk_33M),
    .I      (clk_33M_in));

BUFG BUFG33M (
    .O      (gclk_33M),
    .I      (clk_33M));

OBUF_LVCMOS25 ACECLKEN (
    .O      (ace_clk_en),
    .I      (1'b0));