rx_heartbeat.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: rx_heartbeat.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-10-15 09:06:59-06 $
// /___/   /\    Date Created: May 25, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: rx_heartbeat.v,rcs $
// Revision 1.1  2004-10-15 09:06:59-06  jsnow
// Header update and code optimizations.
//
// Revision 1.0  2004-05-25 13:24:13-06  jsnow
// Initial revision
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
This module is used to generate a strobe signal to an LED to be used as a
heartbeat indicator, showing that the receiver is receiving video. The module
simply takes the TRS signal, decoding externally to this module, uses it as a
clock signal and divides it down to to about 2Hz. The heartbeat output of the
module can then be connected to an LED for a visible heartbeat indicator.

The module divides the TRS signal by 40960. This will result in a fash rate of
between around 2 Hz, depending the video standard being received. The on pulse
has a less than 50% duty cycle.

*/

`timescale 1ns / 1ns

module rx_heartbeat (
    input  wire clk,        // clock input
    input  wire xyz,        // asserted during XYZ word of TRS
    input  wire trs_err,    // asserted if TRS reception error occurs
    output wire heartbeat   // heartbeat output
);

//
// Internal signals
//
wire                ce1;            // stage 1 divider clock enable
wire                stage1;         // stage 1 output
wire                stage2;         // stage 2 output
wire                stage3;         // stage 3 output
wire                stage4;         // stage 4 output
reg [1:0]           sync;           // dual rank synchronizer
reg                 trs_err_latch;  // input to synchronizer
wire                good_trs;       // xyz and not trs_err

//
// Generate a synchronous input to the divider circuit that is asserted when
// the valid XYZ word of a TRS is detected.
//
assign good_trs = xyz & ~trs_err;

always @ (posedge clk or posedge good_trs)
    if (good_trs)
        trs_err_latch <= 1'b1;
    else
        trs_err_latch <= 1'b0;
        
always @ (posedge clk)
    sync <= {sync[0], trs_err_latch};
                
//
// First stage divider
//
assign ce1 = sync[1];

SRL16E srl1 (
    .Q   (stage1),
    .A0  (1'b1),
    .A1  (1'b1),
    .A2  (1'b1),
    .A3  (1'b1),
    .CE  (ce1),
    .CLK (clk),
    .D   (stage1));

// synthesis translate_off
defparam srl1.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl1 is 1

//
// Second stage divider
//   
SRL16E srl2 (
    .Q   (stage2),
    .A0  (1'b1),
    .A1  (1'b1),
    .A2  (1'b1),
    .A3  (1'b1),
    .CE  (ce1 & stage1),
    .CLK (clk),
    .D   (stage2));

// synthesis translate_off
defparam srl2.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl2 is 1
               
//
// Third stage divider
//   
SRL16E srl3 (
    .Q   (stage3),
    .A0  (1'b1),
    .A1  (1'b1),
    .A2  (1'b1),
    .A3  (1'b1),
    .CE  (ce1 & stage1 & stage2),
    .CLK (clk),
    .D   (stage3));

// synthesis translate_off
defparam srl3.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl3 is 1

//
// Fourth stage divider
//   
SRL16E srl4 (
    .Q   (stage4),
    .A0  (1'b1),
    .A1  (1'b0),
    .A2  (1'b0),
    .A3  (1'b1),
    .CE  (ce1 & stage1 & stage2 & stage3),
    .CLK (clk),
    .D   (stage4));

// synthesis translate_off
defparam srl4.INIT = 1;
// synthesis translate_on
// synthesis attribute INIT of srl4 is 1

assign heartbeat = stage4;

endmodule