hdsdi_decoder.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2005 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: hdsdi_decoder.v,rcs $
//  /   /        Date Last Modified:  $Date: 2005-01-14 10:39:19-07 $
// /___/   /\    Date Created: Jan 5, 2005 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: hdsdi_decoder.v,rcs $
// Revision 1.1  2005-01-14 10:39:19-07  jsnow
// Header update.
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

SMPTE 292M-1998 (HD-SDI) is a standard for transmitting high-definition digital 
video over a serial link.

HD-SDI specifies that the serial bit stream shall be encoded in two ways. First,
a generator polynomial of x^9 + x^4 + 1 is used to generate a scrambled NRZ bit
sequence. Next, a generator polynomial of x + 1 is used to produce the final
polarity free NRZI sequence which is transmitted over the physical layer.

The decoder module described in this file sits at the receiving end of the
HD-SDI link and reverses the two encoding steps to extract the original data. 
First, the x + 1 generator polynomial is used to convert the bit stream from 
NRZI to NRZ. Next, the x^9 + x^4 + 1 generator polynomial is used to descramble 
the data.

This module works in parallel on 20-bits at a time. The module treats the data
as a serial bit stream and isn't concerned about where the actual character
boundaries are in the bit stream. 

--------------------------------------------------------------------------------
*/

module hdsdi_decoder (
    clk,                            // input clock
    rst,                            // async reset input
    ce,                             // clock enable input
    d,                              // input data
    q                               // output data
);

// IO definitions   
input               clk;
input               rst;
input               ce;
input   [19:0]      d;
output  [19:0]      q;


// Internal registers 
reg                 prev_d19;       // previous d[19] bit register
reg     [8:0]       prev_nrz;       // holds 9 MSBs from NRZI-to-NRZ for use in next clock cycle
reg     [19:0]      out_reg;

// Internal wires
wire    [28:0]      desc_wide;      // concat of two input words used by descrambler
wire    [19:0]      nrz;            // output of the NRZI-to-NRZ converter

integer             i;              // for loop variable


//
// prev_d19 register
//
// This register holds the MSB of the previous clock period's d input so
// that a 21-bit input vector is available to the NRZI-to-NRZ converter.
// 
always @ (posedge clk or posedge rst)
    if (rst)
        prev_d19 <= 0;
    else if (ce)
        prev_d19 <= d[19];

//
// NRZI-to-NRZ converter
//
// The 20 XOR gates generated by this statement convert the 21-bit wide
// nrzi data to 20 bits of NRZ data. Each bit from the input is XORed with
// the bit that preceded it in the bit stream. The LSB of d is XORed with the 
// MSB of input from the previous clock period that is held in the prev_d19 
// register.
//
assign nrz = d ^ {d[18:0], prev_d19};

//
// prev_nrz Input register of the descrambler
//
// This register is a pipeline delay register which loads from the output of the
// NRZI-to-NRZ converter. It only holds the nine MSBs from the converter which
// get combined with 20-bits coming from the converter on the next clock cycle
// to form a 29-bit wide input vector to the descrambler.
//
always @ (posedge clk or posedge rst)
    if (rst)
        prev_nrz <= 0;
    else if (ce)
        prev_nrz <= nrz[19:11];

assign desc_wide = {nrz, prev_nrz};

// 
// Descrambler
//
// A for loop is used to generate the HD-SDI x^9 + x^4 + 1 polynomial for 
// each of the 20-bits to be output using the 29-bit desc_wide input vector 
// that is made up of the contents of the prev_nrz register and the output of 
// the NRZI-to-NRZ converter.
//
always @ (posedge clk or posedge rst)
    if (rst)
        out_reg <= 0;
    else if (ce)
        for (i = 0; i < 20; i = i + 1)
            out_reg[i] <= desc_wide[i] ^ desc_wide[i + 4] ^ desc_wide[i + 9];
        
assign q = out_reg;

endmodule