multigenhd_logo.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

wire    [7:0]           arom8_out;
wire    [7:0]           arom9_out;
wire    [7:0]           arom10_out;
reg     [7:0]           lrom_out;       // MUX selects between logo ROMs

`ifdef VIRTEX4 
wire    [47:0]          logo_mult_p;
wire    [47:0]          logo_Y_sum;
`else
wire    [14:0]          rom_adr_mult;
wire    [35:0]          logo_mult_p;
wire    [17:0]          logo_Y_sum;
`endif

//
// Video format select input register
//
always @ (posedge clk or posedge rst)
    if (rst)
        std_q <= 0;
    else
        std_q <= std;
        
assign std_change = std != std_q;

//----------------------------------------------------------------------------
// Vertical section
//
multigenHD_vert VERT (
    .clk            (clk),
    .rst            (reset),
    .ce             (ce),
    .std            (std_q),
    .pattern        (pattern),
    .h_counter_lsb  (h_counter_lsb),
    .v_inc          (v_inc),
    .v_band         (v_band),
    .v              (v_int),
    .f              (f_int),
    .first_line     (first_line),
    .y_ramp_inc_sel (y_ramp_inc_sel),
    .line_num       (v_counter));



//----------------------------------------------------------------------------
// Horizontal section
//

multigenHD_horz_logo HORZ (
    .clk            (clk),
    .rst            (reset),
    .ce             (ce),
    .std            (std_q),
    .pattern        (pattern),
    .user_opt       (user_opt),
    .first_line     (first_line),
    .f              (f_int),
    .v_inc          (v_inc),
    .trs            (trs_int),
    .xyz            (xyz_int),
    .h              (h_int),
    .h_region       (h_region),
    .h_counter_lsb  (h_counter_lsb),
    .h_counter      (h_counter));   

//----------------------------------------------------------------------------
// Output section
//

multigenHD_output OUTGEN (
    .clk            (clk),
    .rst            (reset),
    .ce             (ce),
    .h_region       (h_region),
    .v_band         (v_band),
    .h_counter_lsb  (h_counter_lsb),
    .y_ramp_inc_sel (y_ramp_inc_sel),
    .y              (y_int),
    .c              (c_int));

//
// Output registers
//
// These registers delay various output signals so that they all have the same
// amount of delay and are synchronized at the output of the module.
//
always @ (posedge clk or posedge reset)
    if (reset)
        begin
            y <= 0;
            c <= 0;
            f_reg <= 0;
            v_reg <= 0;
            h_reg <= 0;
            trs_reg <= 0;
            xyz_reg <= 0;
            line_num <= 0;
        end
    else if (ce)
        begin
            y <= logo_out_mux_Y; 
            c <= logo_out_mux_C; 
            f_reg <= {f_reg[0], f_int};
            v_reg <= {v_reg[0], v_int};
            h_reg <= {h_reg[0], h_int};
            trs_reg <= {trs_reg[0], trs_int};
            xyz_reg <= {xyz_reg[0], xyz_int};
            line_num <= v_counter;
        end

assign field = f_reg[1];
assign v_blank = v_reg[1];
assign h_blank = h_reg[1];
assign trs = trs_reg[1];
assign xyz = xyz_reg[1];

//
// Reset generator
//
// This circuit keeps the module reset for about 64 clock cycles after the rst
// input to the module goes away. This insures that the module starts up in an
// orderly fashion. Also, the reset signal is asserted whenever the std inputs
// change, insuring that the video pattern generator begins at a good state
// when the video format changes.
//

always @ (posedge clk or posedge rst)
    if (rst)
        delay_rst <= 0;
    else
        delay_rst <= {delay_rst[14:0], 1'b1};

assign reset = rst | ~delay_rst[15] | std_change;

//------------------------------------------------------------------------------
// Logo Generation
//

//
// Decode the video standard and assert the proper type signal. Note that if
// the contents of the video pattern ROMs change, this code may also need to 
// change.
//
always @ *
begin
    is1080i = 1'b0;
    is1080p = 1'b0;
    is720p  = 1'b0;

    case(std_q)
        3'b000: is720p  = 1'b1;
        3'b001: is1080i = 1'b1;
        3'b010: is1080i = 1'b1;
        3'b011: is1080i = 1'b1;
        3'b100: is1080p = 1'b1;
        3'b101: is1080p = 1'b1;
        3'b110: is1080p = 1'b1;
        3'b111: is720p  = 1'b1;
    endcase
end

//
// Implement MUXes that output the starting V, ending V, and starting H
// locations of the logo based on the video standard.
//
always @ *
    if (is1080i)
        begin
            logo_start_v = f_int ? LOGO_START_V1_1080i : LOGO_START_V0_1080i;
            logo_end_v   = f_int ? LOGO_END_V1_1080i   : LOGO_END_V0_1080i;
            logo_start_h = LOGO_START_H_1080;
        end
    else if (is1080p)
        begin
            logo_start_v = LOGO_START_V_1080p;
            logo_end_v   = LOGO_END_V_1080p;
            logo_start_h = LOGO_START_H_1080;
        end
    else
        begin
            logo_start_v = LOGO_START_V_720p;
            logo_end_v   = LOGO_END_V_720p;
            logo_start_h = LOGO_START_H_720;
        end

//
// Generate the logo_en_v and logo_en signals to indicate when the
// active logo area is being generated by the video pattern generator. 
// logo_en_dly is logo_en delayed by one clock cycle to match the latency
// through the block RAMs. logo_en_dly is used to control the video output
// MUXes.
//
assign logo_v_mux = logo_en_v ? logo_end_v : logo_start_v;
assign logo_v_match = logo_v_mux == v_counter;

assign sav = (h_region == HRGN_SAV1) & h_counter_lsb;

always @ (posedge clk)
    if (ce)
        begin
            if (v_int)
                logo_en_v <= 1'b0;
            else if (sav & logo_v_match)
                logo_en_v <= ~logo_en_v;
        end

always @ (posedge clk)
    if (ce)
        begin
            if (h_counter == logo_start_h && logo_en_v)
                logo_en <= 1'b1;
            else if (rom_adr_h == LOGO_WIDTH - 1)
                logo_en <= 1'b0;
        end

always @ (posedge clk)
    if (ce)
        logo_en_dly <= logo_en;

//
// Logo ROM address V counter