📄 multigenhd_logo.v
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//------------------------------------------------------------------------------
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
//------------------------------------------------------------------------------
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
// \ \ Filename: $RCSfile: multigenHD_logo.v,rcs $
// / / Date Last Modified: $Date: 2005-11-10 14:34:33-07 $
// /___/ /\ Date Created: May 25, 2004
// \ \ / \
// \___\/\___\
//
//
// Revision History:
// $Log: multigenHD_logo.v,rcs $
// Revision 1.0 2005-11-10 14:34:33-07 jsnow
// Added support for Virtex-4 DSP48 in logo generation.
//
//------------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------
/*
This is a modification of the multigenHD module from XAPP682 to include the
option to insert a Xilinx logo in the 100% white in the bottom row of the
RP219 color bar pattern. Logo insertion is enabled with the insert_logo input.
This module requires a slightly modified version of the multigen_horz module
that brings the entire horizontal position counter out as a port.
This video pattern generator will generate color bars for the 18 video standards
currently supported by the SMPTE 292M (HD-SDI) video standard. The color bars
comply with SMPTE RP-219 standard color bars, as shown below. This module can
also generate the SMPTE RP-198 HD-SDI checkfield test pattern and 75% color
bars.
|<-------------------------------------- a ------------------------------------->|
| |
| |<----------------------------(3/4)a-------------------------->| |
| | | |
| d | c c c c c c c | d |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+ - - - - -
| | | | | | | | | | ^ ^
| | | | | | | | | | | |
| | | | | | | | | | | |
| | | | | | | | | | | |
| | | | | | | | | | (7/12)b |
| 40% | 75% | YELLOW | CYAN | GREEN | MAGENTA| RED | BLUE | 40% | | |
| GRAY | WHITE | | | | | | | GRAY | | |
| *1 | | | | | | | | *1 | | b
| | | | | | | | | | | |
| | | | | | | | | | | |
| | | | | | | | | | v |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+ - - - |
|100%CYAN| *2 | 75% WHITE |100%BLUE| (1/12)b |
+--------+--------+-----------------------------------------------------+--------+ - - - |
|100%YELO| *3 | Y-RAMP |100% RED| (1/12)b |
+--------+--------+---+-----------------+-------+--+--+--+--+--+--------+--------+ - - - |
| | | | | | | | | | | | |
| 15% | 0% | 100% | 0% |BL|BL|BL|BL|BL| 0% | 15% | (3/12)b |
| GRAY | BLACK | WHITE | BLACK |K-|K |K+|K |K+| BLACK | GRAY | |
| *4 | | | |2%|0%|2%|0%|4%| | *4 | v
+--------+------------+-----------------+-------+--+--+--+--+--+--------+--------+ - - - - -
d (3/2)c 2c (5/6)c c c c c c c d
- - - - -
3 3 3 3 3
*1: The block marked *1 is 40% Gray for a default value. This value may
optionally be set to any other value in accordance with the operational
requirements of the user.
*2: In the block marked *2, the user may select 75% White, 100% White, +I, or
-I.
*3: In the block marked *3, the user may select either 0% Black, or +Q. When the
-I value is selected for the block marked *2, then the +Q signal must be
selected for the *3 block.
*4: The block marked *4 is 15% Gray for a default value. This value may
optionally be set to any other value in accordance with the operational
requirements of the user.
*/
module multigenHD_logo #(parameter VCNT_WIDTH = 11) (
input wire clk, // word-rate clock
input wire rst, // async reset
input wire ce, // clock enable
input wire [2:0] std, // selects video format
input wire [1:0] pattern, // 00 = RP 219 colorbars,
// X1 = RP 198 checkfield,
// 10 = 75% colorbars
input wire [1:0] user_opt, // selects option for the *2 &
// *3 blocks of RP 219
input wire insert_logo, // 1 = insert xilinx logo
output reg [9:0] y, // luma output channel
output reg [9:0] c, // chroma output channel
output wire h_blank, // asserted during h blanking
output wire v_blank, // asserted
output wire field, // indicates current field
output wire trs, // asserted during 4 words of
// TRS symbol,
output wire xyz, // asserted during TRS XYZ word
output reg [VCNT_WIDTH-1:0] line_num // current vertical line number
);
//-----------------------------------------------------------------------------
// Parameter definitions
//
// Define this parameter if, and only if, the target device is Virtex 4.
`define VIRTEX4
//
// This group of parameters defines the bit widths of various fields in the
// module.
//
parameter VID_WIDTH = 10; // Width of video components
parameter HCNT_WIDTH = 12; // Width of h_counter
parameter HRGN_WIDTH = 5; // Width of h_region counter
parameter VRGN_WIDTH = 5; // Width of v_region counter
parameter VBAND_WIDTH = 3; // Width of vband code
parameter VID_MSB = VID_WIDTH - 1; // MS bit # of video data path
parameter VCNT_MSB = VCNT_WIDTH - 1; // MS bit # of v_counter
parameter HCNT_MSB = HCNT_WIDTH - 1; // MS bit # of h_counter
parameter HRGN_MSB = HRGN_WIDTH - 1; // MS bit # of h_region counter
parameter VBAND_MSB = VBAND_WIDTH - 1; // MS bit # of vband code
parameter LOGO_START_H_1080 = 616; // starting h position of logo for 1080i/p/sF
parameter LOGO_START_H_720 = 365; // starting h position of logo for 720p
parameter LOGO_START_V0_1080i = 472; // starting v position of logo for 1080i/sF, F=0
parameter LOGO_START_V1_1080i = 1035; // starting v position of logo for 1080i/sF, F=1
parameter LOGO_END_V0_1080i = 513; // ending v position of logo for 1080i/sF, F=0
parameter LOGO_END_V1_1080i = 1076; // ending v position of logo for 1080i/sF, F=1
parameter LOGO_START_V_1080p = 945; // starting v position of logo for 1080p
parameter LOGO_END_V_1080p = 1027; // ending v position of logo for 1080p
parameter LOGO_START_V_720p = 614; // starting v position of logo for 720p
parameter LOGO_END_V_720p = 696; // ending v position of logo for 720p
parameter LOGO_WIDTH = 274; // width of logo
parameter [HRGN_MSB:0] HRGN_SAV1 = 19;
//-----------------------------------------------------------------------------
// Signal definitions
//
reg [2:0] std_q; // register for std inputs
wire std_change; // difference between std and std_q
wire v_inc; // increments the vertical counter
wire [HRGN_MSB:0] h_region; // modified horizontal region value
wire h_counter_lsb; // LSB of h_counter
wire [VCNT_MSB:0] v_counter; // current line number
wire [HCNT_MSB:0] h_counter;
wire [VBAND_MSB:0] v_band; // current vertical band
wire f_int; // vert section F output
wire v_int; // vert section V output
wire first_line; // vert section output indicating first active
wire y_ramp_inc_sel; // vert section output indicating which Y-Ramp increment value to use
wire trs_int; // horz section TRS output
wire xyz_int; // horz section XYZ output
wire h_int; // horz section H output
wire [VID_MSB:0] y_int; // Y output of output generator
wire [VID_MSB:0] c_int; // C output of output generator
reg [1:0] trs_reg; // TRS signal delay reg
reg [1:0] xyz_reg; // XYZ signal delay reg
reg [1:0] h_reg; // H delay register
reg [1:0] v_reg; // V delay register
reg [1:0] f_reg; // F delay register
reg [15:0] delay_rst; // generates a delayed reset to block RAMs
wire reset; // delayed reset signal
reg is720p; // asserted for 720p
reg is1080i; // asserted for 1080i/sF
reg is1080p; // asserted for 1080p
wire sav; // asserted during second word of SAV
reg [VCNT_MSB:0] logo_start_v; // mux output indicating starting V line of logo
reg [VCNT_MSB:0] logo_end_v; // mux output indicating ending V line of logo
wire [VCNT_MSB:0] logo_v_mux; // muxes logo_start_v and logo_end_v
wire logo_v_match; // v_counter == logo_v_match comparator output
reg [HCNT_MSB:0] logo_start_h; // mux output indicating starting H position of logo
reg [6:0] rom_adr_v; // logo ROM V address counter
reg [8:0] rom_adr_h; // logo ROM H address counter
wire [14:0] rom_adr; // complete logo ROM address
wire [14:0] arom_adr; // equal to rom_adr
wire [14:0] brom_adr; // set to all zeros
reg [3:0] arom_adr_ms_dly;// delayed MSBs of rom address for MUX
reg logo_en_v; // asserted when in logo active region vertically
reg logo_en; // asserted when in logo active region
reg logo_en_dly; // logo_en delayed by one clock cycle
wire [9:0] logo_Y; // logo Y component
wire [9:0] logo_out_mux_Y; // MUX logo Y component with video Y component
wire [9:0] logo_out_mux_C; // MUX logo C component with video C component
wire [17:0] logo_mult_a; // ROM address multiplier input A
wire [17:0] logo_mult_b; // ROM address multiplier input B
wire [35:0] logo_mult2_p; // logo Y scaler mult output
wire [17:0] logo_mult2_a; // logo Y scaler mult input A
wire [17:0] logo_mult2_b; // logo Y scaler mult input B
wire [7:0] arom0_out; // logo ROMs
wire [7:0] arom1_out;
wire [7:0] arom2_out;
wire [7:0] arom3_out;
wire [7:0] arom4_out;
wire [7:0] arom5_out;
wire [7:0] arom6_out;
wire [7:0] arom7_out;
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