hdsdi_rx2.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: hdsdi_rx2.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-12-09 13:56:27-07 $
// /___/   /\    Date Created: May 25, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: hdsdi_rx2.v,rcs $
// Revision 1.1  2004-12-09 13:56:27-07  jsnow
// XAPP577 version 1 release.
//
// Revision 1.0  2004-05-25 13:20:18-06  jsnow
// Initial revision
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

This is a slightly modified version of the hdsdi_rx module from XAPP681. The
line number error checkers have been removed. Both the received line number
values and the internally computed line number values are output on ports.

This module contains the HD-SDI decoder, framer, and CRC checker. The module
processes the received data from the RocketIO transceiver, descrambling it, 
framing it, and checking for CRC errors.
  
Data coming from the RocketIO receiver is fed into the hdsdi_decoder. The
decoder can be bypassed by a MUX if dec_bypass is asserted. The decoded data
is then fed into the hdsdi_framer which searches for TRS symbols and reframes
all subsequent video words once a TRS symbol has been found. After framing,
CRC calculations are done separately on the Y and C channels.

The module has the following control inputs:

dec_bypass: if this input is high, the descrambler is bypassed and the data
goes directly from the rxdata port to the framer. This can be used for
diagnostic purposes.

frame_en: this is the framer enable input. When this input is high, the framer
is allowed to resynchronize to changes in the bit offset of the TRS symbols. If
this input is low, the framer will not resynchronize to new TRS offsets and will
continue to use the previously discovered offset. This input can be used to
filter out erroneous TRS offsets. For example, if the nsp output of the module
is connected to the frame_en input, a single erroneous TRS will not cause the
framer to resynchronize. It takes two consecutive TRS symbols both a different
offsets from the offset currently being used, to cause the framer to 
resynchronize. However, if frame_en is tied high, the framer will immediately
resynchronize to any change in TRS offset.


The module has the following outputs:

c_out, y_out: These 10-bit output ports contain the C and Y channel video data
that has been received, decoded, and framed.

nsp: this is the frame New Start Position output. It is asserted when the
starting position of a TRS is found that doesn't match the offset position
currently being used by the framer. If the frame_en input to the framer is high,
nsp will only be asserted for a few clock cycles as the framer resynchronizes.
If the frame_en input is low, nsp will stay high until the frame_en input goes 
high and a TRS is found, or until a TRS is found that matches the original
offset.

trs: this output is asserted high whenever any of the four words of a TRS
symbol are present on the c_out and y_cout ports.

xyz: this output is asserted high during the XYZ word of any TRS symbol.

eav: this output is asserted high during the XYZ word of an EAV symbol.

sav: this output is asserted high during the XYZ word of an SAV symbol.
 
c_ln, y_ln: these output ports will contain the line number information that
is captured from the incoming video stream. The C and Y channels each have their
own line number values stored in the two words immediately after the EAV symbol.
Normally, the LN values for both channels will be exactly the same.

c_crc_err, y_crc_err: these outputs are asserted when a CRC error is detected.
There are separate outputs for each channel. These outputs will be asserted for
one or more clock cycles when there is a CRC error on a line. When counting
errors using these outputs, the counting logic should count rising edges of
the error outputs, not number of clock cycles the signals are asserted.

std: this 4-bit code from the hd_sdi_autodetect module indicates which video
format it has detected on the input video stream. See the hdsdi_autodetect_ln
module for details.

std_locked: this output is asserted when the hdsdi_autodetect_ln module is
locked to the incoming video stream format.

--------------------------------------------------------------------------------
*/

module hdsdi_rx2 (
    clk,                            // receiver clock
    ce,                             // clock enable
    rst,                            // async reset signal
    dec_bypass,                     // high input bypasses the HD-SDI decoder
    frame_en,                       // framer enable input
    rxdata,                         // input data bus
    c_out,                          // chroma channel data output
    y_out,                          // luma channel data output
    nsp,                            // new start position output
    trs,                            // asserted during TRS symbols
    xyz,                            // asserted during XYZ word of TRS symbols
    eav,                            // asserted during XYZ word of an EAV
    sav,                            // asserted during XYZ word of an SAV
    trs_err,                        // asserted during XYZ when error is detected
    rx_ln,                          // received Y channel line number
    gen_ln,                         // internally generated line number
    gen_ln_valid,                   // internally generated line number is valid
    c_crc_err,                      // C channel CRC error
    y_crc_err,                      // Y channel CRC error
    std,                            // 4-bit output code from video format detector
    std_locked                      // indicates when std is valid
);

// IO definitions   
input               clk;
input               ce;
input               rst;
input               dec_bypass;
input               frame_en;
input   [19:0]      rxdata;
output  [9:0]       c_out;
output  [9:0]       y_out;
output              nsp;
output              trs;
output              xyz;
output              eav;
output              sav;
output              trs_err;
output  [10:0]      rx_ln;
output  [10:0]      gen_ln;
output              gen_ln_valid;
output              c_crc_err;
output              y_crc_err;
output  [3:0]       std;
output              std_locked;

// internal signals
wire    [19:0]      dec_out;            // output of hdsdi_decoder
wire    [19:0]      dec_bypass_mux;     // decoder bypass mux
wire    [3:0]       ad_std;             // std output of hdsdi_autodetect_ln
wire                ad_locked;          // std_locked output of hdsdi_autodetect_ln
wire    [9:0]       framer_c_out;       // C channel out of framer
wire    [9:0]       framer_y_out;       // Y channel out of framer
wire    [10:0]      c_ln_int;           // internal version of c_ln
wire    [10:0]      y_ln_int;           // internal version of y_ln
wire    [10:0]      ln_gen;             // LN value generated by hdsdi_autodetect_ln
wire                ln_valid;           // ln_valid output of hdsdi_autodetect_ln
wire                trs_int;            // internal version of trs
wire                eav_int;
wire                sav_int;
wire                xyz_int;

//
// HD-SDI decoder module
//      
hdsdi_decoder DEC (
    .clk            (clk),
    .rst            (rst),
    .ce             (ce),
    .d              (rxdata),
    .q              (dec_out)
);

//
// Deocoder bypass MUX
//
assign dec_bypass_mux = dec_bypass ? rxdata : dec_out;

//
// HD-SDI framer module
//
hdsdi_framer_mult FRM (
    .clk            (clk),
    .rst            (rst),
    .ce             (ce),
    .d              (dec_bypass_mux),
    .frame_en       (frame_en),
    .c              (framer_c_out),
    .y              (framer_y_out),
    .trs            (trs_int),
    .xyz            (xyz_int),
    .eav            (eav_int),
    .sav            (sav_int),
    .trs_err        (trs_err),
    .nsp            (nsp)   
);


assign c_out = framer_c_out;
assign y_out = framer_y_out;
assign trs = trs_int;
assign eav = eav_int;
assign sav = sav_int;
assign xyz = xyz_int;


//
// Receiver CRC checker
//
hdsdi_rx_crc RX_CRC (
    .clk            (clk),
    .rst            (rst),
    .ce             (ce),
    .c_video        (framer_c_out),
    .y_video        (framer_y_out),
    .trs            (trs_int),
    .c_crc_err      (c_crc_err),
    .y_crc_err      (y_crc_err),
    .c_line_num     (c_ln_int),
    .y_line_num     (y_ln_int)
);


assign rx_ln = y_ln_int;

//
// Video format and line number generator
//
// This module is optional and can be removed to reduce the design size. It
// produces a code indicating which video format is being received. It also
// generates line numbers that can be compared to the received line numbers.
//
hdsdi_autodetect_ln AD (
    .clk            (clk),
    .rst            (rst),
    .ce             (ce),
    .vid_in         (framer_y_out[8:7]),
    .eav            (eav_int),
    .sav            (sav_int),
    .reacquire      (1'b0),
    .std            (ad_std),
    .locked         (ad_locked),
    .ln             (ln_gen),
    .ln_valid       (ln_valid)
);

assign gen_ln = ln_gen;
assign gen_ln_valid = ln_valid;
assign std = ad_std;
assign std_locked = ad_locked;

endmodule