hdsdi_rio_refclk.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

    .TXN                (txn),
    .TXP                (txp),
    .TXRUNDISP          ());
// synthesis attribute ALIGN_COMMA_MSB of RIO is "FALSE"
// synthesis attribute CHAN_BOND_LIMIT of RIO is 16
// synthesis attribute CHAN_BOND_MODE of RIO is "OFF"
// synthesis attribute CHAN_BOND_OFFSET of RIO is 8
// synthesis attribute CHAN_BOND_ONE_SHOT of RIO is "FALSE"
// synthesis attribute CHAN_BOND_SEQ_1_1 of RIO is 00000000000
// synthesis attribute CHAN_BOND_SEQ_1_2 of RIO is 00000000000
// synthesis attribute CHAN_BOND_SEQ_1_3 of RIO is 00000000000
// synthesis attribute CHAN_BOND_SEQ_1_4 of RIO is 00000000000
// synthesis attribute CHAN_BOND_SEQ_2_1 of RIO is 00000000000
// synthesis attribute CHAN_BOND_SEQ_2_2 of RIO is 00000000000
// synthesis attribute CHAN_BOND_SEQ_2_3 of RIO is 00000000000
// synthesis attribute CHAN_BOND_SEQ_2_4 of RIO is 00000000000
// synthesis attribute CHAN_BOND_SEQ_2_USE of RIO is "FALSE"
// synthesis attribute CHAN_BOND_SEQ_LEN of RIO is 1
// synthesis attribute CHAN_BOND_WAIT of RIO is 8
// synthesis attribute CLK_CORRECT_USE of RIO is "FALSE"
// synthesis attribute CLK_COR_INSERT_IDLE_FLAG of RIO is "FALSE"
// synthesis attribute CLK_COR_KEEP_IDLE of RIO is "FALSE"
// synthesis attribute CLK_COR_REPEAT_WAIT of RIO is 1
// synthesis attribute CLK_COR_SEQ_1_1 of RIO is 00000000000
// synthesis attribute CLK_COR_SEQ_1_2 of RIO is 00000000000
// synthesis attribute CLK_COR_SEQ_1_3 of RIO is 00000000000
// synthesis attribute CLK_COR_SEQ_1_4 of RIO is 00000000000
// synthesis attribute CLK_COR_SEQ_2_1 of RIO is 00000000000
// synthesis attribute CLK_COR_SEQ_2_2 of RIO is 00000000000
// synthesis attribute CLK_COR_SEQ_2_3 of RIO is 00000000000
// synthesis attribute CLK_COR_SEQ_2_4 of RIO is 00000000000
// synthesis attribute CLK_COR_SEQ_2_USE of RIO is "FALSE"
// synthesis attribute CLK_COR_SEQ_LEN of RIO is 1
// synthesis attribute COMMA_10B_MASK of RIO is 1111111000
// synthesis attribute CRC_END_OF_PKT of RIO is "K29_7"
// synthesis attribute CRC_FORMAT of RIO is "USER_MODE"
// synthesis attribute CRC_START_OF_PKT of RIO is "K27_7"
// synthesis attribute DEC_MCOMMA_DETECT of RIO is "TRUE"
// synthesis attribute DEC_PCOMMA_DETECT of RIO is "FALSE"
// synthesis attribute DEC_VALID_COMMA_ONLY of RIO is "FALSE"
// synthesis attribute MCOMMA_10B_VALUE of RIO is 1100000000
// synthesis attribute MCOMMA_DETECT of RIO is "FALSE"
// synthesis attribute PCOMMA_10B_VALUE of RIO is 0011111000
// synthesis attribute PCOMMA_DETECT of RIO is "FALSE"
// synthesis attribute RX_BUFFER_USE of RIO is "TRUE"
// synthesis attribute RX_CRC_USE of RIO is "FALSE"
// synthesis attribute RX_DATA_WIDTH of RIO is 2
// synthesis attribute RX_DECODE_USE of RIO is "FALSE"
// synthesis attribute RX_LOSS_OF_SYNC_FSM of RIO is "FALSE"
// synthesis attribute RX_LOS_INVALID_INCR of RIO is 1
// synthesis attribute RX_LOS_THRESHOLD of RIO is 4
// synthesis attribute TERMINATION_IMP of RIO is 50
// synthesis attribute SERDES_10B of RIO is "FALSE"
// synthesis attribute TX_BUFFER_USE of RIO is "TRUE"
// synthesis attribute TX_CRC_FORCE_VALUE of RIO is 11010110
// synthesis attribute TX_CRC_USE of RIO is "FALSE"
// synthesis attribute TX_DATA_WIDTH of RIO is 2
// synthesis attribute TX_DIFF_CTRL of RIO is 800
// synthesis attribute TX_PREEMPHASIS of RIO is 1
// synthesis attribute REF_CLK_V_SEL of RIO is 0
// synthesis translate_off
 defparam RIO.ALIGN_COMMA_MSB="FALSE";
 defparam RIO.CHAN_BOND_LIMIT=16;
 defparam RIO.CHAN_BOND_MODE="OFF";
 defparam RIO.CHAN_BOND_OFFSET=8;
 defparam RIO.CHAN_BOND_ONE_SHOT="FALSE";
 defparam RIO.CHAN_BOND_SEQ_1_1=11'b00000000000;
 defparam RIO.CHAN_BOND_SEQ_1_2=11'b00000000000;
 defparam RIO.CHAN_BOND_SEQ_1_3=11'b00000000000;
 defparam RIO.CHAN_BOND_SEQ_1_4=11'b00000000000;
 defparam RIO.CHAN_BOND_SEQ_2_1=11'b00000000000;
 defparam RIO.CHAN_BOND_SEQ_2_2=11'b00000000000;
 defparam RIO.CHAN_BOND_SEQ_2_3=11'b00000000000;
 defparam RIO.CHAN_BOND_SEQ_2_4=11'b00000000000;
 defparam RIO.CHAN_BOND_SEQ_2_USE="FALSE";
 defparam RIO.CHAN_BOND_SEQ_LEN=1;
 defparam RIO.CHAN_BOND_WAIT=8;
 defparam RIO.CLK_CORRECT_USE="FALSE";
 defparam RIO.CLK_COR_INSERT_IDLE_FLAG="FALSE";
 defparam RIO.CLK_COR_KEEP_IDLE="FALSE";
 defparam RIO.CLK_COR_REPEAT_WAIT=1;
 defparam RIO.CLK_COR_SEQ_1_1=11'b00000000000;
 defparam RIO.CLK_COR_SEQ_1_2=11'b00000000000;
 defparam RIO.CLK_COR_SEQ_1_3=11'b00000000000;
 defparam RIO.CLK_COR_SEQ_1_4=11'b00000000000;
 defparam RIO.CLK_COR_SEQ_2_1=11'b00000000000;
 defparam RIO.CLK_COR_SEQ_2_2=11'b00000000000;
 defparam RIO.CLK_COR_SEQ_2_3=11'b00000000000;
 defparam RIO.CLK_COR_SEQ_2_4=11'b00000000000;
 defparam RIO.CLK_COR_SEQ_2_USE="FALSE";
 defparam RIO.CLK_COR_SEQ_LEN=1;
 defparam RIO.COMMA_10B_MASK=10'b1111111000;
 defparam RIO.CRC_END_OF_PKT="K29_7";
 defparam RIO.CRC_FORMAT="USER_MODE";
 defparam RIO.CRC_START_OF_PKT="K27_7";
 defparam RIO.DEC_MCOMMA_DETECT="TRUE";
 defparam RIO.DEC_PCOMMA_DETECT="FALSE";
 defparam RIO.DEC_VALID_COMMA_ONLY="FALSE";
 defparam RIO.MCOMMA_10B_VALUE=10'b1100000000;
 defparam RIO.MCOMMA_DETECT="FALSE";
 defparam RIO.PCOMMA_10B_VALUE=10'b0011111000;
 defparam RIO.PCOMMA_DETECT="FALSE";
 defparam RIO.RX_BUFFER_USE="TRUE";
 defparam RIO.RX_CRC_USE="FALSE";
 defparam RIO.RX_DATA_WIDTH=2;
 defparam RIO.RX_DECODE_USE="FALSE";
 defparam RIO.RX_LOSS_OF_SYNC_FSM="FALSE";
 defparam RIO.RX_LOS_INVALID_INCR=1;
 defparam RIO.RX_LOS_THRESHOLD=4;
 defparam RIO.TERMINATION_IMP=50;
 defparam RIO.SERDES_10B="FALSE";
 defparam RIO.TX_BUFFER_USE="TRUE";
 defparam RIO.TX_CRC_FORCE_VALUE=8'b11010110;
 defparam RIO.TX_CRC_USE="FALSE";
 defparam RIO.TX_DATA_WIDTH=2;
 defparam RIO.TX_DIFF_CTRL=800;
 defparam RIO.TX_PREEMPHASIS=1;
 defparam RIO.REF_CLK_V_SEL=0;          // Use REFCLKs
// synthesis translate_on

//
// Swap the received data
//
assign rxdata[ 0] = recdata[19];
assign rxdata[ 1] = recdata[18];
assign rxdata[ 2] = recdata[17];
assign rxdata[ 3] = recdata[16];
assign rxdata[ 4] = recdata[15];
assign rxdata[ 5] = recdata[14];
assign rxdata[ 6] = recdata[13];
assign rxdata[ 7] = recdata[12];
assign rxdata[ 8] = recdata[11];
assign rxdata[ 9] = recdata[10];
assign rxdata[10] = recdata[ 9];
assign rxdata[11] = recdata[ 8];
assign rxdata[12] = recdata[ 7];
assign rxdata[13] = recdata[ 6];
assign rxdata[14] = recdata[ 5];
assign rxdata[15] = recdata[ 4];
assign rxdata[16] = recdata[ 3];
assign rxdata[17] = recdata[ 2];
assign rxdata[18] = recdata[ 1];
assign rxdata[19] = recdata[ 0];

//
// Swap the transmit data
//
assign txdata_swap[ 0] = txdata[19];
assign txdata_swap[ 1] = txdata[18];
assign txdata_swap[ 2] = txdata[17];
assign txdata_swap[ 3] = txdata[16];
assign txdata_swap[ 4] = txdata[15];
assign txdata_swap[ 5] = txdata[14];
assign txdata_swap[ 6] = txdata[13];
assign txdata_swap[ 7] = txdata[12];
assign txdata_swap[ 8] = txdata[11];
assign txdata_swap[ 9] = txdata[10];
assign txdata_swap[10] = txdata[ 9];
assign txdata_swap[11] = txdata[ 8];
assign txdata_swap[12] = txdata[ 7];
assign txdata_swap[13] = txdata[ 6];
assign txdata_swap[14] = txdata[ 5];
assign txdata_swap[15] = txdata[ 4];
assign txdata_swap[16] = txdata[ 3];
assign txdata_swap[17] = txdata[ 2];
assign txdata_swap[18] = txdata[ 1];
assign txdata_swap[19] = txdata[ 0];

//
// RocketIO transceiver reset logic
//
always @ (posedge rxusrclk)
    if (~dcm_locked)
        startup_counter <= 0;
    else if (startup_counter != 4'h8)
        startup_counter <= startup_counter + 1;

always @ (posedge rxusrclk or negedge dcm_locked)
    if (~dcm_locked)
        gt_rst <= 1'b1;
    else if (startup_counter == 4'h4)
        gt_rst <= 1'b0;

assign rst_x = gt_rst | rst;
                             

endmodule