hdsdi_rio_refclk.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: hdsdi_rio_refclk.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-08-23 13:06:14-06 $
// /___/   /\    Date Created: May 21, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: hdsdi_rio_refclk.v,rcs $
// Revision 1.1  2004-08-23 13:06:14-06  jsnow
// Comment changes only.
//
// Revision 1.0  2004-05-21 13:56:28-06  jsnow
// Initial Revision
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

This module instantiates a single RocketIO transceiver using the GT_CUSTOM
primitive.

The modules swaps the txdata input vector to account for the fact that the
RocketIO transmitter sends the MSB first, whereas HD-SDI requires that the
LSB to be sent first. It does the same for the rxdata vector from the RocketIO 
receiver.

The module also includes the necessary logic to properly reset the RocketIO
transceiver. The RocketIO module is kept in reset until several clock cycles
after the dcm_locked signal is negated.

Note that this module connects the REFCLK, REFCLK2, BREFCLK, and BREFCLK2 clock
pins. However, it set the REF_CLK_V_SEL attribute of the GT_CUSTOM primitive to
0 so that only the REFCLK and REFCLK2 reference clock inputs are active. To
use the BREFCLK and BREFCLK2 inputs, you must set the REF_CLK_V_SEL attribute
to 1. The BREFCLK/2 inputs are brought out of the module because some early
versions of ISE had problems with placing the RocketIO module if BREFCLK/2
were not brought out to the top level of the design.

--------------------------------------------------------------------------------
*/

module hdsdi_rio_refclk (
    brefclk,                        // BREFCLK  (not used)
    brefclk2,                       // BREFCLK2 (not used)
    refclk,                         // REFCLK
    refclk2,                        // REFCLK2
    refclk_sel,                     // selects between REFCLK and REFCLK2
    rst,                            // reset signal
    loopback_en,                    // loopback enable
    loopback_mode,                  // 0 is serial, 1 is parallel mode
    txinhibit,                      // inhibits transmitter when 1
    txdata,                         // data to be transmitted
    txusrclk,                       // transmitter usr clock
    txusrclk2,                      // transmitter usr clock 2
    rxusrclk,                       // receiver usr clock
    rxusrclk2,                      // receiver usr clock 2
    dcm_locked,                     // DCM for RXUSRCLKs is locked
    rxp,                            // serial input - true
    rxn,                            // serial input - complement
    rxdata,                         // received data from RocketIO receiver
    rxrecclk,                       // clock recovered by RocketIO receiver
    txp,                            // serial output - true
    txn                             // serial output - complement
);

// IO definitions   
input               brefclk;
input               brefclk2;
input               refclk;
input               refclk2;
input               refclk_sel;
input               rst;
input               loopback_en;
input               loopback_mode;
input               txinhibit;
input   [19:0]      txdata;
input               txusrclk;
input               txusrclk2;
input               rxusrclk;
input               rxusrclk2;
input               dcm_locked;
input               rxp;
input               rxn;
output  [19:0]      rxdata;
output              rxrecclk;
output              txp;
output              txn;

// Internal wires
reg                 gt_rst;             // delayed reset signal to satisfy the needs of the RocketIO
wire                rst_x;              // gt_rst or reset
reg     [3:0]       startup_counter;    // used to generate gt_rst
wire    [19:0]      txdata_swap;        // data to be transmitted after bit swapping
wire    [19:0]      recdata;            // received data from RocketIO before bit swapping
wire    [1:0]       loop;               // loopback control signals
wire    [3:2]       rxcharisk_float;    // used to pad rxcharisk output to 4 bits
wire    [31:16]     rxdata_float;       // used to pad rxdata output to 32 bits
wire    [3:2]       rxrundisp_float;    // used to pad rxrundisp output to 4 bits


//
// loopback control signals
//
// Encodes the loopback_en and loopback_mode signals into the two inputs
// needed by the RocketIO to control loopback mode.
//
assign loop[1] = loopback_en & ~loopback_mode;
assign loop[0] = loopback_en & loopback_mode;

//
// RocketIO transceiver
//
// Use the GT_CUSTOM primitive because we need to be able to bypass the 8B10B
// encode/decode functions.
//
GT_CUSTOM RIO (
    .CHBONDI            (4'b0000),
    .CONFIGENABLE       (1'b0),
    .CONFIGIN           (1'b0),
    .ENMCOMMAALIGN      (1'b0),
    .ENPCOMMAALIGN      (1'b0),
    .ENCHANSYNC         (1'b0),
    .LOOPBACK           (loop),
    .POWERDOWN          (1'b0),
    .REFCLK             (refclk),
    .REFCLK2            (refclk2),
    .REFCLKSEL          (refclk_sel),
    .BREFCLK            (brefclk),
    .BREFCLK2           (brefclk2),
    .RXN                (rxn),
    .RXP                (rxp),
    .RXPOLARITY         (1'b0),
    .RXRESET            (rst_x),
    .RXUSRCLK           (rxusrclk),
    .RXUSRCLK2          (rxusrclk2),
    .TXBYPASS8B10B      (4'b0011),
    .TXCHARDISPMODE     ({2'b00, txdata_swap[19], txdata_swap[9]}),
    .TXCHARDISPVAL      ({2'b00, txdata_swap[18], txdata_swap[8]}),
    .TXCHARISK          (4'b0000),
    .TXDATA             ({16'b0, txdata_swap[17:10], txdata_swap[7:0]}),
    .TXFORCECRCERR      (1'b0),
    .TXINHIBIT          (txinhibit),
    .TXPOLARITY         (1'b0),
    .TXRESET            (rst_x),
    .TXUSRCLK           (txusrclk),
    .TXUSRCLK2          (txusrclk2),
    .CHBONDDONE         (),
    .CHBONDO            (),
    .CONFIGOUT          (),
    .RXBUFSTATUS        (),
    .RXCHARISCOMMA      (),
    .RXCHARISK          ({rxcharisk_float[3:2], recdata[19], recdata[9]}),
    .RXCHECKINGCRC      (),
    .RXCLKCORCNT        (),
    .RXCOMMADET         (),
    .RXCRCERR           (),
    .RXDATA             ({rxdata_float[31:16], recdata[17:10], recdata[7:0]}),
    .RXDISPERR          (),
    .RXLOSSOFSYNC       (),
    .RXNOTINTABLE       (),
    .RXREALIGN          (),
    .RXRECCLK           (rxrecclk),
    .RXRUNDISP          ({rxrundisp_float[3:2], recdata[18], recdata[8]}),
    .TXBUFERR           (),
    .TXKERR             (),