phasedethd.v

SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: phasedetHD.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-10-15 09:03:53-06 $
// /___/   /\    Date Created: May 25, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: phasedetHD.v,rcs $
// Revision 1.1  2004-10-15 09:03:53-06  jsnow
// Header update.
//
// Revision 1.0  2004-05-25 13:23:55-06  jsnow
// Initial revision
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

This module is the top level of the phase detector used in conjuction with an
external VCXO and loop filter to implement a PLL for jitter reducing the
recovered clock from the Rocket IO transceiver in a HD-SDI pass-through
application.

*/
module  phasedetHD (
    // inputs
    vco,
    refclk,
    reset,
    //outputs
    mkvcofaster,
    mkvcoslower,
    //test
    vco_tc,
    refclk_tc
);

//----------------------------------------------------------------------------
// Signal declarations
//

input       vco;
input       refclk;
input       reset;
output      mkvcofaster;
output      mkvcoslower;
output      vco_tc;
output      refclk_tc;

//
// Local signals
//
wire    vcounlockedtrig;
wire    vcolockedcntTC;
reg     vcolockdet,vcolockdetR;
reg     vcolocked;
reg [15:0]  vcolockedcnt;



//-----------------------------------------------------------------------------
//trigger pulse for "un-locked detection
//if the clocks are not rolling ie. in locked 
//condition vcolockdet and vcolockdetR should 
//always be the same.
//
always @ (posedge refclk or posedge reset ) begin 
    if (reset) begin
        vcolockdet  <= #1 1'b0 ;
        vcolockdetR <= #1 1'b0 ;
    end
    else begin
        vcolockdet  <= #1 vco_tc ;
        vcolockdetR <= #1 vcolockdet ;
    end
end

assign vcounlockedtrig = vcolockdetR ^ vcolockdet;



//-----------------------------------------------------------------------------
//start a counter, reset if trig occurs, if the counter
//gets to 32K then assumed in locked condition.
//once in locked condition do not allow counter to count any more
//at this point try to lock to data.
//
always @ (posedge refclk or posedge reset ) begin 
    if (reset) begin
        vcolocked   <= #1 1'b0 ;
        vcolockedcnt    <= #1 16'h0000 ;
        end
    else if (vcounlockedtrig & ~vcolockedcntTC) begin
        vcolocked   <= #1 1'b0 ;
        vcolockedcnt    <= #1 16'h0000 ;
        end
    else if (vcolockedcntTC) begin
        vcolocked   <= #1 1'b1 ;
        vcolockedcnt    <= #1 vcolockedcnt ;
        end
    else begin 
        vcolocked   <= #1 1'b0 ;
        vcolockedcnt    <= #1 vcolockedcnt + 1 ;
        end
end


assign vcolockedcntTC = vcolockedcnt[15];


//-----------------------------------------------------------------------------
// phase detector
pd_HD_VCXO pd(
    //inputs
    .vco(vco),
    .refclk(refclk),
    .reset(reset),
    //outputs
    .vcoisfast(mkvcoslower),
    .vcoisslow(mkvcofaster),
    .vco_tc(vco_tc),
    .refclk_tc(refclk_tc)
);

endmodule