fft_tb.v

来自「jpeg压缩中的DCT蝶型算法verilog代码」· Verilog 代码 · 共 56 行

/********************************************************************
        butterfly testbench
********************************************************************/
`timescale 1ns/100ps

`define   CLK_PERIOD   8

module butterfly_tb;
    
//===================================================================
reg   [7:0] in1_re;
reg   [7:0] in1_im;
reg   [7:0] in2_re;   
reg   [7:0] in2_im;
reg   clk;

//===================================================================
// ------------------------------------------------------------------
//
// CLOCK generator 
//
// ------------------------------------------------------------------
initial
begin: clock_generator
    clk = 1'b1;
    forever #(`CLK_PERIOD/2) clk=~clk;
end //clock generator

// ------------------------------------------------------------------
//
// input data generator 
//
// ------------------------------------------------------------------
always @(posedge clk)
begin
    in1_re   <= 8'h24;
    in1_im   <= 0;
    in2_re   <= 8'h17;
    in2_im   <= 0;
end

//===================================================================
butterfly butterfly(.out1_re(out1_re),
                    .out1_im(out1_im),
                    .out2_re(out2_re),
                    .out2_im(out2_im),
                    .in1_re(in1_re),
                    .in1_im(in1_im),
                    .in2_re(in2_re),
                    .in2_im(in2_im),
                    .clk(clk)            
                    );
//==============================================================================
//==============================================================================
//==============================================================================
endmodule