ep931xide.cpp

Cirrus EP9315 wince bsp

	return TRUE;
}

//****************************************************************************
// CEP931xPort::EndDMA
//****************************************************************************
// End the DMA
// 
//
BOOL CEP931xPort::EndDMA() 
{ 
    volatile BYTE            bStatus;

    DEBUGMSG
    ( 
        ZONE_DMA, 
        (
            TEXT("ATAPI:EndDMA\r\n")
        )
    );

	//* * * CAMSDB - Clear the IDE IRQ.
    bStatus = (BYTE)(ATAReadRegister(CSDA_STAT_REG) & 0xFF);

    //
    // Clear the M2M DMA interrupt register. 
    //
    m_pulDmaBase[M2M_INT>>2] = 0;

    //
    // Disable the DMA channel.
    //
    m_pulDmaBase[M2M_CTRL>>2] = 0;

    return TRUE;
}

//****************************************************************************
// CEP931xDisk::AbortDMA
//****************************************************************************
// Aborts the DMA after the DMA has started.
// 
//
BOOL CEP931xPort::AbortDMA() 
{ 
    BOOL    fRet;
    DEBUGMSG
    ( 
        ZONE_DMA, 
        (
            TEXT("ATAPI:AbortDMA\r\n")
        )
    );

    //
    // Clear the status register.
    //
    m_pulDmaBase[M2M_INT>>2] = 0;
    
    //
    // Unlock the Buffers and free the mapped pointers.
    //
    if(m_fAligned)
    {
        fRet = UnlockPages
        ( 
            m_pucDmaBuffer,
            m_ulDmaCount
        );
        ASSERT(fRet);
    }

    //
    // Disable the DMA channel.
    //
    m_pulDmaBase[M2M_CTRL>>2] = 0;

    return TRUE; 
}

//****************************************************************************
// CEP931xDisk::CompleteDMA
//****************************************************************************
// Completes the DMA and cleans up the buffers.
// 
//
BOOL CEP931xPort::CompleteDMA(PSG_BUF pSgBuf, DWORD dwSgCount, BOOL fRead) 
{ 
    ULONG   ulDmaCount;
    ULONG   ulBuffer;
    LPBYTE  pBuffer;
    BOOL    fRet = TRUE;
    LARGE_INTEGER liStart, liCurrent, liEnd;

    DEBUGMSG
    ( 
        ZONE_DMA, 
        (
            TEXT("ATAPI:CompleteDMA\r\n")
        )
    );

    //
    // Unlock the Buffers and free the mapped pointers.
    //
    if(m_fAligned)
    {
        fRet = UnlockPages
        ( 
            m_pucDmaBuffer,
            m_ulDmaCount
        );
        ASSERT(fRet);
    }

    //
    // If the pSgBuf are unaligned, copy the entire buffer to our buffer.
    //
    else if(!m_fAligned && fRead)
    {
	//QueryPerformanceCounter(&liStart);
        ulDmaCount        = 0;
        for (ulBuffer = 0; ulBuffer < dwSgCount; ulBuffer++) 
        {
            pBuffer = (LPBYTE)MapPtrToProcess(pSgBuf[ulBuffer].sb_buf, GetCallerProcess());

			DEBUGMSG( 1, (TEXT("     * * * About to check and possibly do memcopy * * *\r\n")));

			if (pSgBuf[ulBuffer].sb_len >0x8000 || pSgBuf[ulBuffer].sb_len <=0 || pBuffer == NULL || m_pucDmaBuffer == NULL)
				{
				if (pSgBuf[ulBuffer].sb_len >0x8000 || pSgBuf[ulBuffer].sb_len <0)
					{
					DEBUGMSG( 1, (TEXT("     * * * pSgBuf[ulBuffer].sb_len was %ld * * *\r\n"),pSgBuf[ulBuffer].sb_len));
					pSgBuf[ulBuffer].sb_len = 0;
					}

				if (m_pucDmaBuffer == NULL)
					DEBUGMSG( 1, (TEXT("     * * * m_pucDmaBuffer was NULL * * *\r\n")));

				if (pBuffer == NULL)
					DEBUGMSG( 1, (TEXT("     * * * pBuffer was NULL * * *\r\n")));
				}
			else
				memcpy(pBuffer, m_pucDmaBuffer + ulDmaCount, pSgBuf[ulBuffer].sb_len);

            ulDmaCount+= pSgBuf[ulBuffer].sb_len;
        }
    //RETAILMSG( 1, (TEXT("     * * * Unaligned copy in CompleteDMA... * * *\r\n")));

	//QueryPerformanceCounter(&liEnd);

	//liCurrent.QuadPart = (liEnd.QuadPart - liStart.QuadPart);
	//RETAILMSG ( 1, (TEXT("* * * It took %ld uS for CompleteDMA to complete. * * *\r\n"),liCurrent.QuadPart));
	}

    return fRet;
}

//****************************************************************************
// CEP931xDisk::PIOMode
//****************************************************************************
// PIO mode.
// 
//
void CEP931xPort::PIOMode(void)
{

    if(m_bDMAState)
    {
        //
        // Disable the dma.
        //
        *IDE_MDMAOP =  0;
        *IDE_UDMAOP =  0;

        //
        // Disable the IDE channel.
        //
        *IDE_CFG    = IDE_CFG_IDEEN | IDE_CFG_PIOEN | IDE_CFG_PIO4 | (1 <<IDE_CFG_WST_SHIFT);

        //
        // Set the DMA state to false.
        //
        m_bDMAState = FALSE;
    }
}

//****************************************************************************
// CEP931xPort::DumpDmaState
//****************************************************************************
// Dumps the Dma state machine 
// 
//
void CEP931xPort::DumpDmaState(void)
{
    NKDbgPrintfW( L"    M2M_CTRL         = 0x%08x\r\n", m_pulDmaBase[M2M_CTRL>>2]);
    NKDbgPrintfW( L"    M2M_INT          = 0x%08x\r\n", m_pulDmaBase[M2M_INT>>2]);
    NKDbgPrintfW( L"    M2M_STATUS       = 0x%08x\r\n", m_pulDmaBase[M2M_STATUS>>2]);
    NKDbgPrintfW( L"    M2M_BCR0         = 0x%08x\r\n", m_pulDmaBase[M2M_BCR0>>2]);
    NKDbgPrintfW( L"    M2M_BCR1         = 0x%08x\r\n", m_pulDmaBase[M2M_BCR1>>2]);
    NKDbgPrintfW( L"    M2M_SAR_BASE0    = 0x%08x\r\n", m_pulDmaBase[M2M_SAR_BASE0>>2]);
    NKDbgPrintfW( L"    M2M_SAR_BASE1    = 0x%08x\r\n", m_pulDmaBase[M2M_SAR_BASE1>>2]);
    NKDbgPrintfW( L"    M2M_SAR_CURRENT0 = 0x%08x\r\n", m_pulDmaBase[M2M_SAR_CURRENT0>>2]);
    NKDbgPrintfW( L"    M2M_SAR_CURRENT1 = 0x%08x\r\n", m_pulDmaBase[M2M_SAR_CURRENT1>>2]);
    NKDbgPrintfW( L"    M2M_DAR_BASE0    = 0x%08x\r\n", m_pulDmaBase[M2M_DAR_BASE0>>2]);
    NKDbgPrintfW( L"    M2M_DAR_BASE1    = 0x%08x\r\n", m_pulDmaBase[M2M_DAR_BASE1>>2]);
    NKDbgPrintfW( L"    M2M_DAR_CURRENT0 = 0x%08x\r\n", m_pulDmaBase[M2M_DAR_CURRENT0>>2]);
    NKDbgPrintfW( L"    M2M_DAR_CURRENT1 = 0x%08x\r\n", m_pulDmaBase[M2M_DAR_CURRENT1>>2]);
}
//****************************************************************************
// CEP931xPort::DumpIDEState
//****************************************************************************
// 
// 
//
void CEP931xPort::DumpIDEState(void)
{
    NKDbgPrintfW(L"    IDE_CTRL         = 0x%08x\r\n", *IDE_CTRL);
    NKDbgPrintfW(L"    IDE_CFG          = 0x%08x\r\n", *IDE_CFG);
    NKDbgPrintfW(L"    IDE_MDMAOP       = 0x%08x\r\n", *IDE_MDMAOP);
    NKDbgPrintfW(L"    IDE_UDMAOP       = 0x%08x\r\n", *IDE_UDMAOP);
    NKDbgPrintfW(L"    IDE_UDMASTATUS   = 0x%08x\r\n", *IDE_UDMASTATUS);
    NKDbgPrintfW(L"    IDE_UDMADEBUG    = 0x%08x\r\n", *IDE_UDMADEBUG);
    NKDbgPrintfW(L"    IDE_UDMAWFST     = 0x%08x\r\n", *IDE_UDMAWFST);
    NKDbgPrintfW(L"    IDE_UDMARFST     = 0x%08x\r\n", *IDE_UDMARFST);
}


//****************************************************************************
// CEP931xDisk::CEP931xDisk
//****************************************************************************
// Constructor.
// 
//
CEP931xDisk::CEP931xDisk
(
    CEP931xPort *pPort, 
    HKEY    hDevKey
):  CDisk(hDevKey), m_pPort(pPort)  
{

    //
    // We support interrupts and are a 16 bit device.
    //
    m_f16Bit = TRUE;
    m_fInterruptSupported = TRUE;
}

//****************************************************************************
// CEP931xDisk::Init
//****************************************************************************
// Initialization function for CEP931xDisk
// 
//
BOOL CEP931xDisk::Init(HKEY hActiveKey)
{

    BOOL bRet;
	int ThreadPriority;
	static int IterationCount = 0;

    //  Retrieve DeviceID  Number from Registry (0,1,2,3,4,5,6,7).
    //   A Device is specified by three Bits:
    //      Bit 0 - Specify Device on the chanel/port. Master(0)/Slave(1)
    //      Bit 1 - Specify Port/Channel: 0- Primary, 1 - Secondary Port
    //      Bit 3 - Specify Ata Controller/Adapter.
    //
    bRet = AtaGetRegistryValue(m_hDevKey, TEXT("DeviceId"), &m_dwDeviceId);
    
    if(!bRet)
    {
        DEBUGMSG( ZONE_INIT, (TEXT("ATAPIPCI:Init: Missing Device Number in Registry \r\n")));
    }

    //
    // Verify that the DeviceID is in range
    //
    if ((m_dwDeviceId <0) || (m_dwDeviceId >= MAX_ATA_DEVICES))
    {
        DEBUGMSG( ZONE_INIT, (TEXT("ATAPIPCI:Init: Wrong DeviceID in the Registry DeviceId=% \r\n"),m_dwDeviceId));
        bRet = FALSE;
    }

    if(bRet)
    {    
        //
        // Now can configure Port if not configure yet. 
        //
        m_dwDevice = m_dwDeviceId & 1;

        
        //
        // Initialize the base class.
        //
        bRet = CDisk::Init(hActiveKey);
		
		if (bRet == 1)
			++IterationCount;
    }

	//CeSetThreadPriority(GetCurrentThread(), 15);

	ThreadPriority = CeGetThreadPriority(GetCurrentThread());
	DEBUGMSG ( ZONE_INIT, (TEXT("* * * CEP931xDisk thread priority = %d * * *\r\n"),ThreadPriority));

    //
    // Keep this commented out because it will erase your boot sector on the    
    // hard drive.
    //
    //TestRoutines();


    return bRet;
}


//****************************************************************************
// CEP931xDisk::GetBaseStatus
//****************************************************************************
// 
// 
//
BYTE CEP931xDisk::GetBaseStatus()
{
    return(BYTE(ATAReadRegister(CSDA_STAT_REG) & 0xFF));
}

//****************************************************************************
// CEP931xDisk::GetAltStatus
//****************************************************************************
// 
// 
//
BYTE CEP931xDisk::GetAltStatus()
{
    return(BYTE(ATAReadRegister(CSDA_ALT_STAT_REG) & 0xFF));
}

//****************************************************************************
// CEP931xDisk::GetError
//****************************************************************************
// 
// 
//
BYTE CEP931xDisk::GetError()
{
    return(BYTE(ATAReadRegister(CSDA_ERROR_REG) & 0xFF));
}

//****************************************************************************
// CEP931xDisk::GetReason
//****************************************************************************
// 
// 
//
BYTE CEP931xDisk::GetReason()
{
    return(BYTE(ATAReadRegister(CSDA_REASON_REG) & 0xFF));
}

//****************************************************************************
// CEP931xDisk::SelectDevice
//****************************************************************************
// 
// 
//
void CEP931xDisk::SelectDevice()
{
    ATAWriteRegister
    (
        CSDA_DRVHD_REG, 
        (m_dwDevice == 0 ) ? ATA_HEAD_DRIVE_1 : ATA_HEAD_DRIVE_2
    );
}

//****************************************************************************
// CEP931xDisk::WriteDriveController
//****************************************************************************
// Currently the only reason to write the Drive Controller or the alternate 
// Drive Controller is to enable the interrupt.  On the EP931x the interrupt is 
// always enabled inside the conntroller.
// 
//
void CEP931xDisk::WriteDriveController(BYTE bData)
{
    ATAWriteRegister(CSDA_ALT_CTRL_REG, (ULONG) bData);
}

//****************************************************************************
// CEP931xDisk::WriteAltDriveController
//****************************************************************************
// Currently the only reason to write the Drive Controller or the alternate