📄 startup.lst
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ARM macroassembler Page:1
1 00000000 ;**********************************************************************
2 00000000 ;
3 00000000 ; Filename: startup.s
4 00000000 ;
5 00000000 ; Description: Initialization before the MMU gets turned. This is
6 00000000 ; the first code that gets executed.
7 00000000 ;
8 00000000 ; THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
9 00000000 ; ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
10 00000000 ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
11 00000000 ; PARTICULAR PURPOSE.
12 00000000 ;
13 00000000 ; Use of this source code is subject to the terms of the Cirrus end-user
14 00000000 ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
15 00000000 ; If you did not accept the terms of the EULA, you are not authorized to
16 00000000 ; use this source code. For a copy of the EULA, please see the
17 00000000 ; EULA.RTF on your install media.
18 00000000 ;
19 00000000 ; Copyright(c) Cirrus Logic Corporation 2002, All Rights Reserved
20 00000000 ;
21 00000000 ;**********************************************************************
22 00000000
25 00000000 OPT 1 ; reenable listing
26 00000000 OPT 128 ; disable listing of macro expansions
27 00000000
28 00000000
29 00000000 IMPORT SysconSetup
30 00000000 IMPORT EbootMain
31 00000000 IMPORT MMUSetup
32 00000000 IMPORT SdramCfg
33 00000000
34 00000000 ;**********************************************************************
35 00000000 ; StartUp routine to initialize the processor.
36 00000000 ;**********************************************************************
37 00000000 STARTUPTEXT
38 00000000 43 52 55 DCB "CRUS"
53
39 00000004 LEAF_ENTRY StartUp
40 00000004
41 00000004 ;
42 00000004 ; Kill watch dog timer. Before any thing else.
43 00000004 ;
44 00000004 e59f0124 ldr r0, =0x80940000
45 00000008 e59f1124 ldr r1, =0xAA55
46 0000000c e5801000 str r1, [r0]
47 00000010
48 00000010
49 00000010 ;
50 00000010 ; ensure SVC32 mode with IRQ and FIQ disabled
51 00000010 ;
52 00000010 e3a000d3 mov r0, #0xd3
53 00000014 e121f000 msr cpsr_c, r0
54 00000018
55 00000018 ;
56 00000018 ; Check to see if we are executing in flash, if so we need to
57 00000018 ; copy this into sdram.
58 00000018 ;
59 00000018 e35f0206 cmp pc, #0x60000000
60 0000001c 9a00000c bls ExecuteFromRam
61 00000020
62 00000020 ;
63 00000020 ; When Programming SDRAM clear clkset1 so the delay loop have proper
64 00000020 ; delays.
65 00000020 ;
66 00000020 e5801000 str r1, [r0]
67 00000024 e59f010c ldr r0, =0x80930020
68 00000028 e3a01000 ldr r1, =0x0
69 0000002c e5801000 str r1, [r0]
70 00000030
71 00000030
72 00000030 ;
73 00000030 ; Configure SDRAM
74 00000030 ;
75 00000030 eb000000 bl SdramCfg
76 00000034
77 00000034
78 00000034 ;
79 00000034 ; Copy the image to RAM
80 00000034 ;
81 00000034 e3a00206 ldr r0, =0x60000000
82 00000038 e3a01701 ldr r1, =0x40000
83 0000003c e3a0b806 ldr r11, =0x60000
84 00000040 e8b003fc EbootCopyLoop ldmia r0!, {r2-r9}
85 00000044 e8a103fc stmia r1!, {r2-r9}
86 00000048 e151000b cmp r1, r11
87 0000004c 1afffffb bne EbootCopyLoop
88 00000050
89 00000050 e59ff0e8 ldr pc, =ExecuteFromRam
90 00000054
91 00000054
92 00000054 ;
93 00000054 ; create a temporary stack below kernel memory from config.bib
94 00000054 ;
95 00000054 ExecuteFromRam
96 00000054 e59fd0e8 ldr sp, =EbootStack
97 00000058 eb000000 bl SysconSetup
98 0000005c
99 0000005c
100 0000005c ;
101 0000005c ; Initializes the vector table. Incase of spurious vectors.
102 0000005c ;
103 0000005c e59f00e4 ldr r0, =VectorTable
104 00000060 e3a01000 ldr r1, =0x0
105 00000064 e8b003fc ldmia r0!, {r2-r9}
106 00000068 e8a103fc stmia r1!, {r2-r9}
107 0000006c e8b003fc ldmia r0!, {r2-r9}
108 00000070 e8a103fc stmia r1!, {r2-r9}
109 00000074
110 00000074 ;
111 00000074 ; Lets setup the MMU Linear = Physical. This allows us to
112 00000074 ; setup cachable and noncachable areas.
113 00000074 ;
114 00000074 eb000000 bl MMUSetup
115 00000078 ;
116 00000078 ; Branch to eboot main C routine.
117 00000078 ;
118 00000078 eb000000 bl EbootMain
119 0000007c ;
120 0000007c ; KernelStart should never return:
121 0000007c ;
122 0000007c
123 0000007c eafffffe spin b spin
124 00000080
125 00000080 ;*************************************************************************
126 00000080 ; Default vectors
127 00000080 ;
128 00000080 ; We never should hit these vectors, but just in case lets do something
129 00000080 ;
130 00000080 ;*************************************************************************
131 00000080 ResetVector
132 00000080 e59f00b4 ldr r0, =0x808C0000
133 00000084 e3a01052 ldr r1, ='R'
134 00000088 e5801000 STR R1, [R0]
135 0000008c eafffffe b .
136 00000090
137 00000090 e59f00a4 UndefVector ldr r0, =0x808C0000
138 00000094 e3a01055 ldr r1, ='U'
139 00000098 e5801000 STR R1, [R0]
140 0000009c eafffffe b .
141 000000a0
142 000000a0 e59f0094 SWIVector ldr r0, =0x808C0000
143 000000a4 e3a01053 ldr r1, ='S'
144 000000a8 e5801000 STR R1, [R0]
145 000000ac eafffffe b .
146 000000b0
147 000000b0 e59f0084 PrefetchVector ldr r0, =0x808C0000
148 000000b4 e3a01050 ldr r1, ='P'
149 000000b8 e5801000 STR R1, [R0]
150 000000bc eafffffe b .
151 000000c0
152 000000c0 e59f0074 DataAbortVector ldr r0, =0x808C0000
153 000000c4 e3a01044 ldr r1, ='D'
154 000000c8 e5801000 STR R1, [R0]
155 000000cc eafffffe b .
156 000000d0
157 000000d0 e59f0064 FIQVector ldr r0, =0x808C0000
158 000000d4 e3a01046 ldr r1, ='F'
159 000000d8 e5801000 STR R1, [R0]
160 000000dc eafffffe b .
161 000000e0
162 000000e0 e59f0054 IRQVector ldr r0, =0x808C0000
163 000000e4 e3a01049 ldr r1, ='I'
164 000000e8 e5801000 STR R1, [R0]
165 000000ec eafffffe b .
166 000000f0
167 000000f0 VectorTable
168 000000f0 ;
169 000000f0 ; Load value of relative label into program counter, causing jump to
170 000000f0 ; the value stored at the label.
171 000000f0 ; At startup pc is zero 0, loading the value of this lable should
172 000000f0 ; place pc in the area of 0x80090000. LDR is PC Relative.
173 000000f0 ;
174 000000f0 e59ff018 ldr PC, Reset_Addr
175 000000f4 e59ff018 ldr PC, Undefined_Addr
176 000000f8 e59ff018 ldr PC, SWI_Addr
177 000000fc e59ff018 ldr PC, Prefetch_Addr
178 00000100 e59ff018 ldr PC, Abort_Addr
179 00000104 e1a00000 nop ; Reserved vector
180 00000108 e59ff018 ldr PC, IRQ_Addr
181 0000010c e59ff018 ldr PC, FIQ_Addr
182 00000110
183 00000110 ;; these DCDs (below) have to remain here for the LDRs above to be able to jump
184 00000110 ;; with offset
185 00000110
186 00000110 ExceptionVectorTable
187 00000110
188 00000110 00000080 Reset_Addr DCD ResetVector
189 00000114 00000090 Undefined_Addr DCD UndefVector
190 00000118 000000a0 SWI_Addr DCD SWIVector
191 0000011c 000000b0 Prefetch_Addr DCD PrefetchVector
192 00000120 000000c0 Abort_Addr DCD DataAbortVector
193 00000124 00000000 DCD 0
194 00000128 000000e0 IRQ_Addr DCD IRQVector
195 0000012c 000000d0 FIQ_Addr DCD FIQVector
196 00000130 VectorTableEnd
197 00000130
198 00000130 80940000 *literal pool: constant
198 00000134 0000aa55 *literal pool: constant
198 00000138 80930020 *literal pool: constant
198 0000013c 808c0000 *literal pool: constant
198 00000140 00000054 *literal pool: symbol: ExecuteFromRam + 0x0
198 00000144 00008000 *literal pool: symbol: EbootStack + 0x0
198 00000148 000000f0 *literal pool: symbol: VectorTable + 0x0
198 AREA |.KDATA|,DATA,NOINIT
199 00000000
200 00000000 ;*****************************************************************************
201 00000000 ;
202 00000000 ; The MMU level one page table.
203 00000000 ;
204 00000000 ;*****************************************************************************
205 00000000 00 00 00 EbootStackStart % 0x8000
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