📄 sdramcfg.lst
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ARM macroassembler Page:1
1 00000000 ;**********************************************************************
2 00000000 ;
3 00000000 ; Filename: sdramcfg.s
4 00000000 ;
5 00000000 ; Description: Configures SDRAM.
6 00000000 ;
7 00000000 ; THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
8 00000000 ; ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
9 00000000 ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
10 00000000 ; PARTICULAR PURPOSE.
11 00000000 ;
12 00000000 ; Use of this source code is subject to the terms of the Cirrus end-user
13 00000000 ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
14 00000000 ; If you did not accept the terms of the EULA, you are not authorized to
15 00000000 ; use this source code. For a copy of the EULA, please see the
16 00000000 ; EULA.RTF on your install media.
17 00000000 ;
18 00000000 ; Copyright(c) Cirrus Logic Corporation 2002, All Rights Reserved
19 00000000 ;
20 00000000 ;**********************************************************************
21 00000000
24 00000000 OPT 1 ; reenable listing
25 00000000 OPT 128 ; disable listing of macro expansions
26 00000000
27 00000000 GLOBALCFG_INIT EQU 0x00000001
28 00000000 GLOBALCFG_MRS EQU 0x00000002
29 00000000 GLOBALCFG_SMEMBUSY EQU 0x00000020
30 00000000 GLOBALCFG_LCR EQU 0x00000040
31 00000000 GLOBALCFG_REARBEN EQU 0x00000080
32 00000000 GLOBALCFG_CLKSHUTDOWN EQU 0x40000000
33 00000000 GLOBALCFG_CKE EQU 0x80000000
34 00000000
35 00000000
36 00000000 REFRESH_MASK EQU 0x0000FFFF
37 00000000
38 00000000 BOOTSTATUS_WIDTH_32 EQU 0x00000002
39 00000000 BOOTSTATUS_WIDTH_16 EQU 0x00000001
40 00000000 BOOTSTATUS_WIDTH_8 EQU 0x00000000
41 00000000 BOOTSTATUS_WIDTH_MASK EQU 0x00000003
42 00000000 BOOTSTATUS_MEDIA EQU 0x00000004
43 00000000
44 00000000 DEVCFG_EXTBUSWIDTH EQU 0x00000004
45 00000000 DEVCFG_BANKCOUNT EQU 0x00000008
46 00000000 DEVCFG_SROM512 EQU 0x00000010
47 00000000 DEVCFG_SROMLL EQU 0x00000020
48 00000000 DEVCFG_2KPAGE EQU 0x00000040
49 00000000 DEVCFG_SFCONFIGADDR EQU 0x00000080
50 00000000 DEVCFG_CASLAT_MASK EQU 0x00070000
51 00000000 DEVCFG_CASLAT_2 EQU 0x00010000
52 00000000 DEVCFG_CASLAT_3 EQU 0x00020000
53 00000000 DEVCFG_CASLAT_4 EQU 0x00030000
54 00000000 DEVCFG_CASLAT_5 EQU 0x00040000
55 00000000 DEVCFG_CASLAT_6 EQU 0x00050000
56 00000000 DEVCFG_CASLAT_7 EQU 0x00060000
57 00000000 DEVCFG_CASLAT_8 EQU 0x00070000
58 00000000 DEVCFG_WBL EQU 0x00080000
59 00000000 DEVCFG_RASTOCAS_MASK EQU 0x00300000
60 00000000 DEVCFG_RASTOCAS_2 EQU 0x00200000
61 00000000 DEVCFG_RASTOCAS_3 EQU 0x00300000
62 00000000 DEVCFG_AUTOPRECHARGE EQU 0x01000000
63 00000000
64 00000000 ;****************************************************************************
65 00000000 ; Delay200 - Delays200 us
66 00000000 ;
67 00000000 ; = 200uS / 2 (Instructions/ Loop) * 150 (nS/Instruction)
68 00000000 ;
69 00000000 ; = 700
70 00000000 ;
71 00000000 ; Uses r0
72 00000000 ;****************************************************************************
73 00000000 MACRO
74 00000000 Delay200
75 00000000 mov r0, #700
76 00000000 200 subs r0, r0, #1
77 00000000 bne %b200
78 00000000 MEND
79 00000000
80 00000000 ;****************************************************************************
81 00000000 ; Delay80 - Delays 80 Clocks
82 00000000 ;
83 00000000 ;
84 00000000 ; Uses r0
85 00000000 ;****************************************************************************
86 00000000 MACRO
87 00000000 Delay80
88 00000000 mov r0, #80
89 00000000 80 subs r0, r0, #1
90 00000000 bne %b80
91 00000000 MEND
92 00000000
93 00000000 TEXTAREA
94 00000000 EXPORT SdramCfg
95 00000000 LEAF_ENTRY SdramCfg
96 00000000
97 00000000 ;
98 00000000 ; Initialize the SDRAM Configuration
99 00000000 ;
100 00000000 e59f0090 ldr r0, =(DEVCFG_BANKCOUNT :or: DEVCFG_SROMLL :or: DEVCFG_CA
SLAT_2 :or: DEVCFG_RASTOCAS_2 )
102 00000004 e59f1090 ldr r1, =0x8006001C
103 00000008 e5810000 str r0, [r1]
104 0000000c
105 0000000c Delay200
106 00000018 ;
107 00000018 ; Set the Initialize and MRS bits (issue continuous NOP commands (INIT & MRS set))
108 00000018 ;
109 00000018 e3a0010e ldr r0, =(GLOBALCFG_INIT :or: GLOBALCFG_MRS :or: GLOBALCFG_C
KE)
111 0000001c e59f107c ldr r1, =0x80060004
112 00000020 e5810000 str r0, [r1]
113 00000024
114 00000024 Delay200
115 00000030
116 00000030 ;
117 00000030 ; Clear the MRS bit to issue a precharge all.
118 00000030 ;
119 00000030 e3a00106 ldr r0, =(GLOBALCFG_INIT :or: GLOBALCFG_CKE)
120 00000034 e5810000 str r0, [r1]
121 00000038
122 00000038 ;
123 00000038 ; Temporarily set the refresh timer to 0x10. Make it really low so that auto refresh
124 00000038 ; cycles are generated. is refreshed.
125 00000038 ;
126 00000038 e3a00010 ldr r0, =0x10
127 0000003c e59f1060 ldr r1, =0x80060008
128 00000040 e5810000 str r0, [r1]
129 00000044
130 00000044 Delay80
131 00000050
132 00000050 e3a00f81 ldr r0, =0x204
133 00000054 e59f1048 ldr r1, =0x80060008
134 00000058 e5810000 str r0, [r1]
135 0000005c
136 0000005c ;
137 0000005c ; Select mode register update mode
138 0000005c ;
139 0000005c e3a0010a ldr r0, =(GLOBALCFG_CKE :or: GLOBALCFG_MRS)
140 00000060 e59f1038 ldr r1, =0x80060004
141 00000064 e5810000 str r0, [r1]
142 00000068
143 00000068 ; *******************************************************************
144 00000068 ;
145 00000068 ; Program the SDRAM mode register using the row information.
146 00000068 ;
147 00000068 ; | | | |
148 00000068 ; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+
149 00000068 ; |13|12|11|10|09|08|07|06|05|04|03|02|01|00|
150 00000068 ; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+
151 00000068 ; +---------+------+ +---+--+ + +--+--+
152 00000068 ; | | | |
153 00000068 ; Must Be Zero | | |
154 00000068 ; | | |
155 00000068 ; | | |
156 00000068 ; LTMODE ---------------+ | |
157 00000068 ; | |
158 00000068 ; Wrap type ---------------------+ |
159 00000068 ; |
160 00000068 ; CAS Latency ---------------------------+
161 00000068 ;
162 00000068 ; *******************************************************************
163 00000068 ;
164 00000068 ; Row Column mapping for 256Meg X 16 Bits X 2. SROM Look Alike mode
165 00000068 ;
166 00000068 ; B1 B0 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
167 00000068 ;
168 00000068 ; Row/Bank A23 A22 A27 A26 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
169 00000068 ;
170 00000068 ; Col A23 A22 AP A25 A24 A09 A08 A07 A06 A05 A04 A03 A02
171 00000068 ;
172 00000068 ; *******************************************************************
173 00000068 ; Sets all four banks using - Cas latency 2
174 00000068 ; - Wrap type sequential
175 00000068 ; - Burst Length 4
176 00000068 ;
177 00000068 ; *******************************************************************
178 00000068 e3a01b22 ldr r1, =0x0008800
179 0000006c e5910000 ldr r0, [r1]
180 00000070
181 00000070 e59f1030 ldr r1, =0x0408800
182 00000074 e5910000 ldr r0, [r1]
183 00000078
184 00000078 e59f102c ldr r1, =0x0808800
185 0000007c e5910000 ldr r0, [r1]
186 00000080
187 00000080 e59f1028 ldr r1, =0x0C08800
188 00000084 e5910000 ldr r0, [r1]
189 00000088
190 00000088 ;
191 00000088 ; Select mode register update mode
192 00000088 ;
193 00000088 e3a00102 ldr r0, =GLOBALCFG_CKE
194 0000008c e59f100c ldr r1, =0x80060004
195 00000090 e5810000 str r0, [r1]
196 00000094 e1a0f00e mov pc, lr
197 00000098
198 00000098 END
199 00000098 00210028 *literal pool: constant
199 0000009c 8006001c *literal pool: constant
199 000000a0 80060004 *literal pool: constant
199 000000a4 80060008 *literal pool: constant
199 000000a8 00408800 *literal pool: constant
199 000000ac 00808800 *literal pool: constant
199 000000b0 00c08800 *literal pool: constant
Assembly terminated, errors: 0, warnings: 0
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