📄 cache.lst
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ARM macroassembler Page:1
1 00000000 ;
2 00000000 ; Copyright (c) Microsoft Corporation. All rights reserved.
3 00000000 ;
4 00000000 ;
5 00000000 ; Use of this source code is subject to the terms of the Microsoft end-user
6 00000000 ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
7 00000000 ; If you did not accept the terms of the EULA, you are not authorized to use
8 00000000 ; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
9 00000000 ; install media.
10 00000000 ;
11 00000000 ; -*-Text-*-
12 00000000 ;
13 00000000 ; $Revision: 1.1.1.1 $
14 00000000 ; $Author: rgorsegn $
15 00000000 ; $Date: 2002/06/28 19:39:49 $
16 00000000 ;
17 00000000 ; Cache920t.s - cache control routines for an ARM920T processor
18 00000000 ;
19 00000000 ; Copyright (c) 1998, 1999 ARM Limited
20 00000000 ; All Rights Reserved
21 00000000 ;
22 00000000
25 00000000 OPT 1 ; reenable listing
26 00000000 OPT 128 ; disable listing of macro expansions
27 00000000
28 00000000 INCLUDE armmacros.s
1 00000000 ;
2 00000000 ; Copyright (c) Microsoft Corporation. All rights reserved.
3 00000000 ;
4 00000000 ;
5 00000000 ; Use of this source code is subject to the terms of the Microsoft end-user
6 00000000 ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
7 00000000 ; If you did not accept the terms of the EULA, you are not authorized to use
8 00000000 ; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
9 00000000 ; install media.
10 00000000 ;
11 00000000
12 00000000 ;/***********************************************************************
13 00000000 ; Copyright (c) ARM Limited 1998. All rights reserved.
14 00000000 ;
15 00000000 ; NOTE: The CALL and CALLEQ macros shouldn't be used in OS startup code
16 00000000 ; before the MMU is enabled since in the Thumbing case it relies
17 00000000 ; on an absolute address which will be virtual in the case of the
18 00000000 ; OS code and if the MMU isn't enabled, all branches should be
19 00000000 ; relative (or a computed physical address).
20 00000000 ;
21 00000000 ;***********************************************************************/
22 00000000
23 00000000 IF Thumbing
54 00000000 ELSE
55 00000000
56 00000000 MACRO
57 00000000 CALL $Fn
58 00000000 bl $Fn
59 00000000 MEND
60 00000000
61 00000000 MACRO
62 00000000 CALLEQ $Fn
63 00000000 bleq $Fn
64 00000000 MEND
65 00000000
66 00000000 MACRO
67 00000000 RETURN
68 00000000 mov pc, lr
69 00000000 MEND
70 00000000
71 00000000 MACRO
72 00000000 RETURN_EQ
73 00000000 moveq pc, lr
74 00000000 MEND
75 00000000
76 00000000 MACRO
77 00000000 RETURN_NE
78 00000000 movne pc, lr
79 00000000 MEND
80 00000000
81 00000000 ENDIF
82 00000000
83 00000000 END
29 00000000
30 00000000 TEXTAREA
31 00000000
32 00000000 ;++
33 00000000 ; Routine Description:
34 00000000 ; Sets the C and B bits to be used to build page tables
35 00000000 ;
36 00000000 ; C and B bits are part of the page table entries and control write through vs.
37 00000000 ; write back cache modes, cacheability, and write buffer use. Note that C
38 00000000 ; and B bit functionality is processor specific and different for the 720,
39 00000000 ; 920, and SA1100. Consult the CPU hardware manual for the CPU
40 00000000 ; in question before altering these bit configurations!!
41 00000000 ; This default configuration (C=B=1)works on all current ARM CPU's and gives
42 00000000 ; the following behaviour
43 00000000 ; ARM720: write through, write buffer enabled
44 00000000 ; ARM920: write back cache mode
45 00000000 ; SA1100: write back, write buffer enabled
46 00000000 ;
47 00000000 ; The four valid options are:
48 00000000 ; ARM_NoBits 0x00000000
49 00000000 ; ARM_CBit 0x00000008
50 00000000 ; ARM_BBit 0x00000004
51 00000000 ; ARM_CBBits 0x0000000C
52 00000000 ;
53 00000000 ; Syntax:
54 00000000 ; DWORD OEMARMCacheMode(void);
55 00000000 ;
56 00000000 ; Arguments:
57 00000000 ; -- none --
58 00000000 ;
59 00000000 ; Return Value:
60 00000000 ; r0 must contain the desired C and B bit configuration. See description above
61 00000000 ; for valid bit patterns.
62 00000000 ;
63 00000000 ; Caution:
64 00000000 ; The value placed in r0 MUST be an immediate data value and NOT a predefined
65 00000000 ; constant. This function is called at a point in the boot cycle where the
66 00000000 ; memory containing predefined constants has NOT been initialized yet.
67 00000000 ; --
68 00000000 LEAF_ENTRY OEMARMCacheMode
69 00000000 e3a0000c mov r0, #0x0C
70 00000004 RETURN
71 00000008
72 00000008 ;++
73 00000008 ; Routine Description:
74 00000008 ; Flush and invalidate the Instruction & Data TLBs for the ARM920
75 00000008 ;
76 00000008 ; Syntax:
77 00000008 ; void TLBClear(void);
78 00000008 ;
79 00000008 ; Arguments:
80 00000008 ; -- none --
81 00000008 ;
82 00000008 ; Return Value:
83 00000008 ; -- none --
84 00000008 ;--
85 00000008 LEAF_ENTRY TLBClear
86 00000008 ee080f15 mcr p15, 0, r0, c8, c5, 0 ; Invalidate I tlb
87 0000000c ee080f16 mcr p15, 0, r0, c8, c6, 0 ; Invalidate D tlb
88 00000010 RETURN
89 00000014
90 00000014
91 00000014 ;++
92 00000014 ; Routine Description:
93 00000014 ; Flush and invalidate the Instruction Cache for ARM920
94 00000014 ;
95 00000014 ; Syntax:
96 00000014 ; void FlushICache(void);
97 00000014 ;
98 00000014 ; Arguments:
99 00000014 ; -- none --
100 00000014 ;
101 00000014 ; Return Value:
102 00000014 ; -- none --
103 00000014 ;--
104 00000014 LEAF_ENTRY FlushICache
105 00000014 ee070f15 mcr p15, 0, r0, c7, c5, 0 ; flush the icache
106 00000018 RETURN
107 0000001c
108 0000001c ;++
109 0000001c ; Routine Description:
110 0000001c ; Clean and invalidate the Data Cache
111 0000001c ;
112 0000001c ; The following code is called to flush the dcache on the ARM920. It
113 0000001c ; does a clean and invalidate on each cache line using the index and
114 0000001c ; segment.
115 0000001c ;
116 0000001c ; Syntax:
117 0000001c ; void FlushDCache(void);
118 0000001c ;
119 0000001c ; Arguments:
120 0000001c ; -- none --
121 0000001c ;
122 0000001c ; Return Value:
123 0000001c ; -- none --
124 0000001c ; r0..r1 junk
125 0000001c ; CC flags junk
126 0000001c ;--
127 0000001c LEAF_ENTRY FlushDCache
128 0000001c
129 0000001c ; r1 holds the associativity field
130 0000001c ; r2 holds the size field
131 0000001c ; r3 holds the line length field
132 0000001c ; r4 is a temporary
133 0000001c ; r5 holds the number of segments - 1
134 0000001c ; lr holds associativity - 1
135 0000001c
136 0000001c e92d4030 stmfd sp!, {r4, r5, lr}
137 00000020
138 00000020 ee100f30 mrc p15, 0, r0, c0, c0, 1 ; read the cache shape register
139 00000024
140 00000024 ; extract associativity from bits 15 to 17
141 00000024 e1a017a0 mov r1, r0, lsr #15
142 00000028 e2011007 and r1, r1, #7
143 0000002c
144 0000002c ; extract cache size from bits 18 to 20
145 0000002c e1a02920 mov r2, r0, lsr #18
146 00000030 e2022007 and r2, r2, #7
147 00000034 e2822009 add r2, r2, #9 ; smallest size is 512 bytes
148 00000038
149 00000038 ; extract line length from bits 12 and 13
150 00000038 e1a03620 mov r3, r0, lsr #12
151 0000003c e2033003 and r3, r3, #3
152 00000040 e2833003 add r3, r3, #3 ; smallest line is 8 bytes
153 00000044
154 00000044 ; calculate the number of segments
155 00000044 e0424001 sub r4, r2, r1
156 00000048 e0444003 sub r4, r4, r3
157 0000004c e3a05001 mov r5, #1
158 00000050 e1a05415 mov r5, r5, lsl r4
159 00000054 e2455001 sub r5, r5, #1
160 00000058
161 00000058 ; calculate the associativity - 1
162 00000058 e3a0e001 mov lr, #1
163 0000005c e1a0e11e mov lr, lr, lsl r1
164 00000060 e24ee001 sub lr, lr, #1
165 00000064
166 00000064 ; r1 holds the shift amount for the associativity
167 00000064 ; r2 holds the segment number
168 00000064 ; r3 holds the shift for the segment
169 00000064 ; r4 is a temporary
170 00000064
171 00000064 e2611020 rsb r1, r1, #32
172 00000068 ee070f9a mcr p15, 0, r0, c7, c10, 4 ; drain write buffer
173 0000006c
174 0000006c camloop
175 0000006c e1a0011e mov r0, lr, lsl r1 ; CAM index
176 00000070 e1a02005 mov r2, r5
177 00000074 blockloop
178 00000074 e1804312 orr r4, r0, r2, lsl r3 ; OR in segment number
179 00000078 ee074f5e mcr p15, 0, r4, c7, c14, 2
180 0000007c ee070f9a mcr p15, 0, r0, c7, c10, 4 ; drain write buffer
181 00000080 e2522001 subs r2, r2, #1
182 00000084 5afffffa bpl blockloop
183 00000088
184 00000088 e25ee001 subs lr, lr, #1
185 0000008c 5afffff6 bpl camloop
186 00000090
187 00000090 IF Thumbing
190 00000090 ELSE
191 00000090 e8bd8030 ldmfd sp!, {r4, r5, pc}
192 00000094 ENDIF
193 00000094
194 00000094 END
Assembly terminated, errors: 0, warnings: 0
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