📄 prac9_232_0115k.lst
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128 910 sfrw FCTL1 = (0x0128);
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12a 912 sfrw FCTL2 = (0x012A);
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12c 914 sfrw FCTL3 = (0x012C);
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59 958 sfrb CACTL1 = (0x0059);
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5a 960 sfrb CACTL2 = (0x005A);
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5b 962 sfrb CAPD = (0x005B);
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1a0 1001 sfrw ADC12CTL0 = (0x01A0);
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1a2 1003 sfrw ADC12CTL1 = (0x01A2);
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1a4 1005 sfrw ADC12IFG = (0x01A4);
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1a6 1007 sfrw ADC12IE = (0x01A6);
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1a8 1009 sfrw ADC12IV = (0x01A8);
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140 1018 sfrw ADC12MEM0 = (0x0140);
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142 1020 sfrw ADC12MEM1 = (0x0142);
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144 1022 sfrw ADC12MEM2 = (0x0144);
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146 1024 sfrw ADC12MEM3 = (0x0146);
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148 1026 sfrw ADC12MEM4 = (0x0148);
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14a 1028 sfrw ADC12MEM5 = (0x014A);
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14c 1030 sfrw ADC12MEM6 = (0x014C);
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14e 1032 sfrw ADC12MEM7 = (0x014E);
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150 1034 sfrw ADC12MEM8 = (0x0150);
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152 1036 sfrw ADC12MEM9 = (0x0152);
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154 1038 sfrw ADC12MEM10 = (0x0154);
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156 1040 sfrw ADC12MEM11 = (0x0156);
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158 1042 sfrw ADC12MEM12 = (0x0158);
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15a 1044 sfrw ADC12MEM13 = (0x015A);
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15c 1046 sfrw ADC12MEM14 = (0x015C);
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15e 1048 sfrw ADC12MEM15 = (0x015E);
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80 1057 sfrb ADC12MCTL0 = (0x0080);
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81 1059 sfrb ADC12MCTL1 = (0x0081);
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82 1061 sfrb ADC12MCTL2 = (0x0082);
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83 1063 sfrb ADC12MCTL3 = (0x0083);
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84 1065 sfrb ADC12MCTL4 = (0x0084);
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85 1067 sfrb ADC12MCTL5 = (0x0085);
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86 1069 sfrb ADC12MCTL6 = (0x0086);
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87 1071 sfrb ADC12MCTL7 = (0x0087);
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88 1073 sfrb ADC12MCTL8 = (0x0088);
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89 1075 sfrb ADC12MCTL9 = (0x0089);
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8a 1077 sfrb ADC12MCTL10 = (0x008A);
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8b 1079 sfrb ADC12MCTL11 = (0x008B);
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8c 1081 sfrb ADC12MCTL12 = (0x008C);
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8d 1083 sfrb ADC12MCTL13 = (0x008D);
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8e 1085 sfrb ADC12MCTL14 = (0x008E);
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8f 1087 sfrb ADC12MCTL15 = (0x008F);
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2 ;******************************************************************************
3 ; MSP-Test44x Demo - USART0 115200 UART Echo ISR, DCO SMCLK
4 ;
5 ; Description; Echo a received character, RX ISR used. Normal mode is LPM0,
6 ; USART0 RX interrupt triggers TX Echo.
7 ; ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = UCLK0 = DCOCLK = 1048576
8 ; Baud rate divider with 1048576hz = 1048576Hz/115200 ~ 9.1 (009h|08h)
9 ;
10 ;
11 ; MSP430F449
12 ; -----------------
13 ; /|\| XIN|-
14 ; | | | 32768Hz
15 ; --|RST XOUT|-
16 ; | |
17 ; | P2.4|----------->
18 ; | | 115200 - 8N1
19 ; | P2.5|<-----------
20 ;
21
22 ;------------------------------------------------------------------------------
23 .pseg code, abs=01100h ; Program Start
24 ;------------------------------------------------------------------------------
1100 3140000a 25 RESET mov.w #0A00h,SP ; Initialize '449 stackpointer
1104 b0120e11 26 call #Init_Sys ;
27 ;
1108 72d01000 28 Mainloop bis.b #((0x0010)),SR ; Enter LPM0
110c fd3f 29 jmp Mainloop ; Do nothing
30 ;
31 ;------------------------------------------------------------------------------
32 Init_Sys; Initalize MSP430 system
33 ;------------------------------------------------------------------------------
110e b240805a2001 34 StopWDT mov.w #(0x5A00)+(0x0080),&WDTCTL ; Stop WDT
1114 f2d020005300 35 SetupFLL bis.b #(0x20),&FLL_CTL0 ; Configure load caps
111a f24020007100 36 SetupUART1 mov.b #(0x20),&U0TCTL ; UCLK = SMCLK
1120 f24010007000 37 mov.b #(0x10),&U0CTL ; 8-bit characters *SWRST*
1126 f24009007400 38 mov.b #009h,&U0BR0 ; 1MHz 115200
112c c2437500 39 mov.b #000h,&U0BR1 ; 1MHz 115200
1130 f2400a007300 40 mov.b #00Ah,&U0MCTL ; modulation
1136 f2d0c0000400 41 bis.b #(0x80)+(0x40),&ME1 ; Enable USART0 TXD/RXD
113c f2d040000000 42 bis.b #(0x40),&IE1 ; Enable USART0 RX interrupt
1142 f2d030002e00 43 SetupP3 bis.b #030h,&P2SEL ; P2.4,5 = USART0 TXD/RXD
1148 f2d010002a00 44 bis.b #010h,&P2DIR ; P2.4 = output direction
114e 32d2 45 eint ; General enable interrupts
1150 3041 46 ret ; Return from subroutine
47 ;
48 ;------------------------------------------------------------------------------
49 USART0RX_ISR; Echo back RXed character, confirm TX buffer is ready first
50 ;------------------------------------------------------------------------------
1152 f2b080000200 51 TX0 bit.b #(0x80),&IFG1 ; USART0 TX buffer ready?
1158 fc27 52 jz TX0 ; Jump if TX buffer not ready
115a d24276007700 53 mov.b &U0RXBUF,&U0TXBUF ; TX -> RXed character
1160 0013 54 reti ;
55 ;
56 ;------------------------------------------------------------------------------
57 ; Interrupt Vectors Used MSP430x44x
58 ;------------------------------------------------------------------------------
59 .pseg rx_vector, abs=0FFF2h ;
fff2 5211 60 .data USART0RX_ISR ; USART0 receive
61 .pseg reset_vector, abs=0FFFEh ;
fffe 0011 62 .data RESET ; POR, ext. Reset, Watchdog
63 end
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