do.do

VHDL程序

# build dir for compile result
vlib work

# compile design
vcom  pll.vhd

# compile test platform
vcom  test_pll.vhd

# simulation
vsim  work.test_pll

# open test windows
view wave
view signals

# signal of test platform
add wave /test_pll/clk_in  
add wave /test_pll/data_in   
add wave /test_pll/clk_out
add wave /test_pll/state
add wave /test_pll/data_out
run 30 ms